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Clock feed-through analysis in switched-capacitor integrator transmission gates switches

Shakeri, M ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1109/ECTICON.2009.5137057
  3. Publisher: 2009
  4. Abstract:
  5. Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the validity of extracted equations. ©2009 IEEE
  6. Keywords:
  7. Clock feed ; Clock signal ; CMOS technology ; Comprehensive analysis ; Falling edge ; Input signal ; Output errors ; Sigma Delta modulator ; Signal processing applications ; Switch parameters ; Switched capacitor circuits ; Switched capacitor integrator ; Transmission gate ; Capacitance ; Capacitors ; Circuit simulation ; Clocks ; CMOS integrated circuits ; Delta sigma modulation ; Information technology ; Modulation ; Signal processing ; Switches ; Switching circuits ; Modulators
  8. Source: 2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009, Chonburi, 6 May 2009 through 9 May 2009 ; Volume 1 , 2009 , Pages 500-503 ; 9781424433889 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/5137057