Sharif Digital Repository

In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with... 

This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is... 

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

First we discuss briefly the importance of time and time keeping, explaining the basic functioning of clocks in general and of atomic clocks based on Ramsey interferometry in particular. The usefulness of cold atoms is discussed, as well as their limits if Bose-Einstein condensates are used. We study as an alternative a different cold-atom regime: the Tonks-Girardeau (TG) gas of tightly confined and strongly interacting bosons. The TG gas is reviewed and then generalized for two-level atoms. Finally, we explore the combination of Ramsey interferometry and TG gases. © 2008 IOP Publishing Ltd  

A new family of sampled-data filters in which accuracy is a function of the ratio of the resistors is introduced. It is shown that this structure is suitable for low-voltage high-speed applications. A biquad filter with a quality factor of 10 and a clock frequency of 60MHz consuming only 2mW power is also presented  

The effect of clock skew and duty-cycle on the performance of high-Q N-phase band-pass filters (BPFs) have been examined in this paper. Following a mathematical approach and using the analytical derivations carried out, the effects of such non-idealities as clock skew and duty-cycle error are determined in an N-path filter. It is analytically proved that image signals from all integer multiples of the clock signal, rather than just those at (1 ± kN) multiples of the clock signal, land atop the wanted RF spectrum. In a real world clock generator, with non-idealities in effect, filtering property and proper behavior of the filter is adversely affected. Finally, system level simulation along... 

Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit... 

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045 μm2 silicon area. © 2005 IEEE  

In this paper, a new all optical phase-locked loop (OPLL) is proposed and analyzed. The scheme relies on using two optical Kerr shutters to reveal the OPLL's error signal. The set of optical Kerr shutters and the subsequent low-speed photodetectors realize two nonlinear cross-correlations between the local clock pulse stream (called pump in Kerr shutter notations) and the time-shifted replicas of the incoming received data signal (called probe). The outputs of the cross-correlators are subtracted to form the error signal of the OPLL. We characterize the mathematical structure of the proposed OPLL and identify its two intrinsic sources of phase noise, namely, randomness of the received... 

In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably... 

In this paper, we analyze and discuss the performance limits of optical clock recovery systems using a phase-locked loop (PLL) structure with nonlinear two-photon absorption (TPA) phase detection scheme. The motivation in analyzing the aforementioned optical PLL with TPA receiver structure is due to a recent successful experiment reported in [8]. We characterize the mathematical structure of PLLs with TPA, so as to evaluate the performance limits on optical clock recovery mechanism. More specifically, we identify two intrinsic sources of phase noise in the system namely, the ON-OFF nature of the incoming data pulses and the detector's shot noise that ultimately limit the performance of the... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

A novel N-path filter using a complex impedance is designed to replace the frontend SAW filters in receivers with on-chip bandpass filters. It is demonstrated that the center frequency of the filter can be tuned solely by changing the value of some capacitances without the need to change the clock frequency. In addition, thanks to the use of smaller capacitors, the silicon area is reduced compared to similar designs. The high-Q bandpass filter is realized utilizing two gyrators and an arrangement of four baseband capacitors with NMOS switches, driven by 4-phase 25% duty cycle clock signals. This paper also analyzes the performance of the proposed filter against imperfections such as thermal... 

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

This paper assesses message missing failures in a FlexRay-based network. The assessment is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller; the parts are: controller host interface, protocol operation control, coding and decoding unit, media access control and clock synchronization process. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. This HDL model of the controller is exploited to setup a FlexRay-based network composed of four nodes. The results of fault injection show that about 35% of faults led to the message missing failures. The controller host interface and the clock...