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sigma-delta-modulator
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Relaxed timing issue in global feedback paths of unity-STF SMASH sigma delta modulator architecture
, Article ARPN Journal of Engineering and Applied Sciences ; Volume 12, Issue 17 , 2017 , Pages 4872-4876 ; 18196608 (ISSN) ; Sadughi, S ; Sharif University of Technology
Abstract
This Paper presents a practical way to improve signal bandwidth and resolution in a Sturdy Multi-Stage Noise- Shaping (SMASH) sigma delta modulator. In this way, the processing timing issue in the critical paths of the proposed architecture has been relaxed due to the shifting delay of the modulator loop filter of each stage to the its feedback path. The proposed Unity-STF SMASH architecture, which is realized with several efficient techniques, would be robust to circuit non-idealities such as finite op-amp DC gain. Furthermore the topology can be implemented by a fewer active blocks, suitable it for low power, high operation speed applications. © 2006-2017 Asian Research Publishing Network...
Design of a High Resolution Sigma-Delta Modulator
, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosro (Supervisor)
Abstract
Sigma-delta modulators have largely been implemented as discrete-time (DT) circuits because of their low sensitivity to circuit nonidealities, and their frequency scaling specification, however a continuous-time (CT) design offers significant advantage in the design of high accuracy, high speed analog to digital converters (ADC). A CT design allows for relaxed amplifier(s) bandwidth and power requirements, which enables the realization of high accuracy modulators with bandwidths of several megahertz at low power consumption. Furthermore CT modulators provide inherent anti-aliasing filtering which becomes especially important at low oversampling ratios. This thesis reports the design of a...
Performance improvement of an optimal family of exponentially accurate sigma delta modulator
, Article International Conference on Signal Processing Proceedings, ICSP, 24 October 2010 through 28 October 2010, Beijing ; 2010 , Pages 1-4 ; 9781424458981 (ISBN) ; Beygiharchegani, S ; Marvasti, F ; Sharif University of Technology
2010
Abstract
In this paper a new iterative method is used to convert analog signals to digital (A/D) using sigma delta modulator (SDM). If intelligent reconstruction technique is used for decoding, either signals with higher bandwidth can be digitized or simpler circuitry can be utilized. An optimal family of SDM has recently been devised in order to improve performance of A/D converters. In this work, we improve performance of A/D converters even more, by combining this optimal family of SDM with iterative methods
A sigma-delta analog to digital converter based on iterative algorithm
, Article Eurasip Journal on Advances in Signal Processing ; Volume 2012, Issue 1 , 2012 ; 16876172 (ISSN) ; Ghorbani, M ; Marvasti, F ; Sharif University of Technology
2012
Abstract
In this article, we present a new iterative algorithm aimed at improving the performance of the sigma-delta analog to digital (A/D) converter. We subject the existing sigma-delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma-delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to...
Improved unity-STF sturdy MASH ΣΔ modulator for low-power wideband applications
, Article Electronics Letters ; Volume 51, Issue 23 , November , 2015 , Pages 1941-1942 ; 00135194 (ISSN) ; Sadughi, S ; Sharif University of Technology
Institution of Engineering and Technology
2015
Abstract
A novel sturdy multi-stage noise-shaping sigma-delta modulator that cancels the first-stage quantisation error at the output of the modulator is presented. Since any stage of the modulator has unity signal transfer function, the modulator would be very robust to circuit non-idealities such as finite op-amp gain. Furthermore, the signal processing timing issue in the critical paths of the proposed topology has been relaxed due to shifting the delay of the last integrator to the feedback path of the modulator. Moreover, this topology can be implemented in the circuit level by a fewer active blocks. Therefore, it practically would be suitable for low-voltage and low-oversampling applications....
Performance improvement of level-crossing A/D converters
, Article 2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications, ICT-MICC 2007, Penang, 14 May 2007 through 17 May 2007 ; February , 2007 , Pages 438-441 ; 1424410940 (ISBN); 9781424410941 (ISBN) ; Marvasti, F ; Sharif University of Technology
2007
Abstract
Level Crossing (LC) Analog-to-Digital converters have been suggested as an asynchronous alternative to conventional schemes. It is our intention to improve the performance of these LC converters. In this paper, we also suggest alternative adaptive and multi-level adaptive LC schemes and use an iterative method to drastically improve the performance of LC converters. The impressive improvement of these schemes make LC converters a potential competitor to other conventional A/D converters such as Sigma Delta Modulators (SDM). ©2007 IEEE
Continuous-time/discrete-time (CT/DT) cascaded sigma-delta modulator for high resolution and wideband applications
, Article WMED 2010 - 8th IEEE Workshop on Microelectronics and Electron Devices, 16 April 2010 through 16 April 2010 ; April , 2010 , Pages 33-36 ; 9781424465750 (ISBN) ; Sadeghi, K. H ; Ay, S. U ; Sharif University of Technology
2010
Abstract
This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW
A 12 Bit Delta-Sigma Modulator For Wireless Applications
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Analog to digital converters are one of the most important component of Bluetooth and GSM receivers. The pipeline and Successive Approximation Register (SAR) ADCs are mainly used in these receivers. However, the pipeline ADCs consume lots of power and SAR ADCs suffer the resolution in advanced technologies. On the other hand, the Delta-Sigma ADCs are capable of achieving high resolution with a low power. So in this thesis, the various kinds and different implementations of Delta-Sigma Modulators are introduced. The system level design and the conversion between Discrete-Time Modulators and Continuous-Time Modulators are explained. The non-ideality effects such as limited gain and bandwidth...
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application
, Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively
Clock feed-through analysis in switched-capacitor integrator transmission gates switches
, Article 2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009, Chonburi, 6 May 2009 through 9 May 2009 ; Volume 1 , 2009 , Pages 500-503 ; 9781424433889 (ISBN) ; Torkzadeh, P ; Shariati Samani, S ; Sharif University of Technology
2009
Abstract
Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the...
An iterative signal recovery technique capable of decreasing the lossy effects of codecs
, Article 2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications, ICT-MICC 2007, Penang, 14 May 2007 through 17 May 2007 ; February , 2007 , Pages 107-112 ; 1424410940 (ISBN); 9781424410941 (ISBN) ; Marvasti, F ; Sharif University of Technology
2007
Abstract
In this paper applications of an iterative method in some signal recovery problems are introduced. It is proved that the distorting effect of linear operators can be removed completely using the iterative scheme. The inverse of monotonic functions can also be made indirectly by the method. A novel approach for separating the messages of different subscribers in a CDMA network will be proposed as well, relying on the recursive approach. It would be shown that Sigma Delta Modulated signals can be decoded via the iterative procedure. We will prove both analytically and with simulations that a broad class of nonlinear operators including speech and image codecs can be approximately inverted with...