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Design considerations for A 1.5-V, 10.7-MHz bandpass GM-C filter in A 0.6-UM standard CMOS techology
, Article Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 25 May 2003 through 28 May 2003 ; Volume 1 , 2003 , Pages I521-I524 ; 02714310 (ISSN) ; Atarodi, S. M ; Sharif University of Technology
2003
Abstract
A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The...
A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer
, Article APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; 2008 , Pages 1383-1386 ; 9781424423422 (ISBN) ; Atarodi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
2008
Abstract
A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE
A 1.8-V high-speed 13-bit pipelined analog to digital converter for digital IF applications
, Article Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 25 May 2003 through 28 May 2003 ; Volume 1 , 2003 , Pages I885-I888 ; 02714310 (ISSN) ; Mehrmanesh, S ; Vahidfar, M. B ; Atarodi, M ; Sharif University of Technology
2003
Abstract
A 1.8-v 13-bit 25MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.18um CMOS technology. The proposed new high speed low power class AB opamp makes it possible to achieve requirements of 13-bit resolution and settling in 12ns within 0.01% accuracy. An optimum architecture for noise and power consideration is also selected to reduce power. Total Power dissipation is about 82 mw from a single 1.8 v supply, where INL and DNL are 0.7 LSB and 0.6 LSB respectively. SNDR of 75.5 dB is achieved
A low power 25 MS/S 12-bit pipelined analog to digital converter for wireless applications
, Article 2003 Southwest Symposium on Mixed-Signal Design, SSMSD 2003, 23 February 2003 through 25 February 2003 ; 2003 , Pages 38-42 ; 0780377788 (ISBN); 9780780377783 (ISBN) ; Mehrmanesh, S ; Vahidfar, M. B ; Safarian, A. Q ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2003
Abstract
A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 μm CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12 bit resolution and settling in 20 ns within 0.05% accuracy. However, pipeline ADCs are tolerant to comparator's offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total power dissipation is about 76 mW from a single 3 V supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. A SNDR of 70.1 dB is achieved. © 2003 IEEE
A very low power CMOS, 1.5V, 2.5GHz prescaler
, Article 2002 45th Midwest Symposium on Circuits and Systems, Tulsa, OK, 4 August 2002 through 7 August 2002 ; Volume 3 , 2002 , Pages III378-III380 ; Sharif University of Technology
2002
Abstract
A very low power CMOS, 1.5V, 2.5GHz prescaler was designed. Implemented in 0.25u standard CMOS technology, this prescaler can operate up to 3GHz range. The prescaler consists of three delay flip flops (DFF) that work synchronously with RF sinusoidal clock and divides by 4 or 5 according to control signal
A 1.5-V supply, 10.7-MHz, bandpass gm-C filter in a 0.6μm standard CMOS technology
, Article 14th International Conference on Microelectronics, ICM 2002, 11 December 2002 through 13 December 2002 ; Volume 2002-January , 2002 , Pages 46-49 ; 0780375734 (ISBN) ; Atarodi, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2002
Abstract
A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE
A 1.8V high dynamic range CMOS Gm-c filter for portable video systems
, Article 14th International Conference on Microelectronics, ICM 2002, 11 December 2002 through 13 December 2002 ; Volume 2002-January , 2002 , Pages 38-41 ; 0780375734 (ISBN) ; Aslanzadeh, H. A ; Vahidfar, M. B ; Atarodi, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2002
Abstract
A 4th order, 5 MHz, lowpass Butterworth Gm-c filter has been combined with a low noise low-voltage amplifier to form a lowpass filter for video applications. In this filter an improved transconductor and a powerful method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the filter is -77 dB for 1 Vppd input signal. Input referred noise is 40 nV/√Hz in the worst case. All the circuits are designed based on a 0.25 μm CMOS process technology with a single 1.8 V supply. © 2002 IEEE
A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology
, Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier Ltd
2019
Abstract
A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The...
12 bits, 40MS/s, low power pipelined SAR ADC
, Article Midwest Symposium on Circuits and Systems ; Aug , 2014 , p. 841-844 ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method
A method for noise reduction in active-rc circuits
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 58, Issue 12 , 2011 , Pages 906-910 ; 15497747 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
Abstract
A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology
An analytic approach used to design a low power and low phase noise CMOS LC oscillator
, Article 2004 IEEE International Frequency Control Symposium and Exposition. A Conference of the IEEE Ultrasonics, Ferroelectrics, and Frequency Control Society (UFFC-S), Montreal, 23 August 2004 through 27 August 2004 ; 2005 , Pages 432-435 ; Behroozi, H ; Yuhas M.P ; Sharif University of Technology
2005
Abstract
An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS LC oscillator is discussed. The phase noise performance for this kind of oscillator is predicted by using a simplified model. This method enables us to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the presented method is demonstrated by designing an LC CMOS oscillator in a 0.24μm CMOS technology. The predictions obtained from the derived expressions are in good agreement with simulation results over a wide range of the supply voltage. © 2004 IEEE
A 1.5V 150MS/s current-mode sample-and-hold circuit
, Article 2005 European Conference on Circuit Theory and Design, Cork, 28 August 2005 through 2 September 2005 ; Volume 2 , 2005 , Pages 91-94 ; 0780390660 (ISBN); 9780780390669 (ISBN) ; Rajaee, O ; Jahanian, A ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power
A novel nano-scaled SRAM cell
, Article World Academy of Science, Engineering and Technology ; Volume 65 , 2010 , Pages 172-174 ; 2010376X (ISSN) ; Sahebi, M. R ; Manzuri Shalmani, M. T ; Sharif University of Technology
Abstract
To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode
Design and Implementation of Protected Smart High Side and Low Side Switch and Drivers in 0.18um HV BCD CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
In this thesis, two types of smart switch & driver chips are designed in 0.18 um HV BCD technology; low side driver and high side driver. These drivers are smart, because of having various types of protection and detection circuits, which protect switch, driver and connected load, versus errors that can be occurred by the user or other environmental effects. The protection circuits are battery over & under voltage shutdown, current limit, inductive load clamper and thermal shutdown. Load status is checked by status detection circuit and reported to user by one bit flag. Battery voltage can vary from 7 V to 40 V and output current is limited to 2 A. Designed high side and low side drivers are...
A low complexity architecture for the cell search applied to the LTE systems
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; Dec , 2012 , Pages 300-303 ; 9781467312615 (ISBN) ; Sharifan, G ; Amini, Y ; Shabany, M ; Sharif University of Technology
2012
Abstract
Cell search is a crucial process in the synchronization procedure for the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) system. In this paper, a high-speed, low-complexity and reliable architecture is proposed for both steps of cell search: sector ID and cell ID group detection. For the sector ID detection, two novel methods, sign-bit reduction and wise resource sharing, are proposed. In addition, for the cell ID group detection, we proposed an algorithm based on the Maximum Likelihood Sequence Detection (MLSD) called 'sign-bit MLSD'. Simulations show that the proposed methods result in more than 90% reduction in area compared to the state-of-the-art. We designed and...
A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18μm CMOS
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Seville, Seville, 9 December 2012 through 12 December 2012 ; 2012 , Pages 157-160 ; 9781467312615 (ISBN) ; Fotowat Ahmady, A ; Jenabi, M ; Sharif University of Technology
2012
Abstract
A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using...
New operational transconductance amplifiers using current boosting
, Article Midwest Symposium on Circuits and Systems ; 2012 , Pages 109-112 ; 15483746 (ISSN) ; 9781467325264 (ISBN) ; Lazarjan, V. K ; HajSadeghi, K ; Sharif University of Technology
2012
Abstract
New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method
Down-conversion self-oscillating mixer by using CMOS technology
, Article Proceedings - 2012 IEEE 8th International Colloquium on Signal Processing and Its Applications, CSPA 2012 ; 2012 , Pages 33-36 ; 9781467309615 (ISBN) ; Zahedi, A ; Sabaghi, M ; Ameri, S. R. H ; Niyakan, M ; Sharif University of Technology
2012
Abstract
In this paper a self-oscillating mixer is presented fundamental signal generated by the oscillator subcircuit in the mixing process. The oscillator core consumes 3mA of current from a 1.8 V DC supply and results in an output power of -0.867 dBm per oscillator, and a measured phase noise of -91, -102 and -108 dBc/Hz at 100 KHz, 600 KHz and 1 MHz from the carrier, respectively. In the mixing process the proposed mixer achieved IIP3 of 0 dBm with conversation gain of 1.93 dB. The circuit was designed and simulated in 0.18-μm CMOS technology by ADS2010
A low-power current reuse CMOS RF front-end for GPS applications
, Article 2011 IEEE International RF and Microwave Conference, RFM 2011 - Proceedings, 12 December 2011 through 14 December 2011, Seremban ; 2011 , Pages 416-419 ; 9781457716294 (ISBN) ; Fotowat Ahmady, A ; Sharif University of Technology
Abstract
A very low-power RF front-end based on a new current reuse QLMV cell (Quadrature VCO-LNA-Mixer) is proposed for GPS applications. The front-end, designed in 0.18μm CMOS technology, provides improved performance characteristics while consuming only 1 mA current. Simulation results are presented and compared with recently published works in the field
Single event upset immune latch circuit design using C-element
, Article Proceedings of International Conference on ASIC, 25 October 2011 through 28 October 2011, Xiamen ; 2011 , Pages 252-255 ; 21627541 (ISSN) ; 9781612841908 (ISBN) ; Tabandeh, M ; Sharif University of Technology
2011
Abstract
Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in...