Sharif Digital Repository

Computationally exhaustive time-domain Monte Carlo (MC) simulations are commonly conducted to obtain the static characteristics of a residual analog-to-digital converter (ADC) (e.g., pipelined ADC) for the calculation of the integral nonlinearity (INL) and differential nonlinearity (DNL). In this brief, a new ultrahigh-speed, yet precise, behavioral-level dc characterization algorithm for residual-based ADC is introduced. The algorithm derives the transition points of a given stage of the ADC based on the random parameters of that stage. Then, it merges the dc characteristics of all stages together to extract detailed dc input-output characteristics for the entire ADC. Then, the exact amount... 

Signal to Noise and Distortion Ratio (SNDR) is widely chosen for dynamic characterization of ADC. For pipelined ADC in which the inner circuits' errors accumulate at the output, analysis of the origins of SNDR and its characterization can be very hard. However, due to a relationship between maximum INL of ADC and the distortion in its output codes, SNDR can be derived as a function of maximum INL value and its position in output codes. Utilizing this relationship, this paper develops two methods for SNDR enhancement that do not cost much power. The 50k sampled Monte-Carlo simulation in the behavioral level indicates 75% increase in the possibility of having SNDR > 60db just by utilizing... 

This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE  

Bi-directional RSFQ benefits from using both positive and negative SFQ pulses to manipulate and transfer digital data. This allows more flexibility in the design of simpler circuits with enhanced performance. On the other hand, using the AC bias current, one can replace on-chip resistive current distributors with inductors. This resembles RQL logic, but in contrast to RQL, it is possible to use the well-established standard RSFQ cells in bi-directional RSFQ. These two advantages (energy-efficient computation and flexibility in design) make bi-directional RSFQ a powerful tool in next-generation supercomputers and also compatible with ultra-low-temperature quantum computers. In this work, to... 

This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This approach is based on the differential configuration for the quantizer while maintains its inherent dynamic element matching property. Consuming no additional power and area compared to the conventional scheme, this architecture can eliminate the even orders of harmonic distortion and achieve higher linearity. Theoretical analysis for signal to quantization noise, power and area consumption and mismatch effect is provided. To illustrate the effectiveness of the new architecture in continuous time modulators, a modulator with 640 MHz sampling rate utilizing the mentioned quantizer is simulated in... 

A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE  

This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18um CMOS process, the 12-bits, 40MS/sec ADC core consumes 7mW from a 1.8V supply  

In this paper a theoretical comparison between the performance of switched-capacitor (SC) and switched-current (SI) pipeline analog-to-digital converters (ADCs) is presented. Power dissipation and die area of SC and SI implementations are compared based on linearity and noise constraints. It is shown that if nonlinearity errors of the class AB SI ADCs are removed by calibration, their performance prevails that of the SC ADCs. Also it is shown that class AB SI ADCs occupy less die area than SC ADCs for a given resolution. © 2007 IEEE  

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after... 

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©... 

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

In theory, diffusion and perfusion information in MRI maps can be combined to yield morphological information, such as capillary density, volume and possibly capillary plasma velocity. This paper suggests a new method for determination of mean radius, length and capillary density in normal regions using diffusion and perfusion MRI. Mean Transit Time (MTT), Cerebral Blood Volume (CBV), Apparent Diffusion Coefficient (ADC), pseudo-diffusion coefficient (D*) and ΔR2 and ΔR2* values were utilized to calculate mean radius, length and capillary density. To verify the proposed theory, a special protocol was designed and tested on normal regions of a male Wistar rat using obtained functions. Mean... 

In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

This paper proposes an Age-Dependent Clustering (ADC) structure to be used for prognostics. To achieve this aim, a step-by-step methodology is introduced, that includes clustering, reproduction, mapping, and finally estimation of Remaining Useful Life (RUL). In the mapping step, a neural fitting tool is used. To clarify the age-based clustering concept, the main elements of the ADC model is discussed. A Genetic algorithm (GA) is used to find the elements of the optimal model. Lastly, the fuzzy technique is applied to modify the clustering. By investigating a case study on the health monitoring of some turbofan engines, the efficacy of the proposed method is demonstrated. The results showed...