Sharif Digital Repository

This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This approach is based on the differential configuration for the quantizer while maintains its inherent dynamic element matching property. Consuming no additional power and area compared to the conventional scheme, this architecture can eliminate the even orders of harmonic distortion and achieve higher linearity. Theoretical analysis for signal to quantization noise, power and area consumption and mismatch effect is provided. To illustrate the effectiveness of the new architecture in continuous time modulators, a modulator with 640 MHz sampling rate utilizing the mentioned quantizer is simulated in... 

A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©... 

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit... 

In this paper, an optimal down sampler is used for Associate Discrete Circuit (ADC) based modeling and simulation of basic switching converters. Characteristic equation of backward Euler based discrete model of the circuit is used to find the value for down sampling. Using ADC modeling, fixed admittance matrix can be achieved for modeling switching converters and using down sampler, additional switch and diode current oscillations are minimized. Real-time digital simulation of buck converter using ADC with down sampler method is implemented on a Field Programmable Gate Array (FPGA) and the results are those expected without additional numerical oscillations. Based on the place-and-route... 

This paper presents a methodology for implementing of the mathematical model of H-Bridge converter in an FPGA-based Real-Time simulator. Furthermore, it introduces a new method for choosing parameters of the Associate Discrete Circuit (ADC) model of semiconductor switches. The ADC-based model allows obtaining a fixed topology irrespective of switches states for the power electronic converters in the digital simulation. Backward-Euler based discretized state space matrix (SSM) of the circuit used for ADC parameter. Choosing appropriate switch parameter is based on 1) reducing the distance of SSM eigenvalues from origin in z-Plane to reduce settling-Time of system response; and 2) reducing the... 

In this paper a theoretical comparison between the performance of switched-capacitor (SC) and switched-current (SI) pipeline analog-to-digital converters (ADCs) is presented. Power dissipation and die area of SC and SI implementations are compared based on linearity and noise constraints. It is shown that if nonlinearity errors of the class AB SI ADCs are removed by calibration, their performance prevails that of the SC ADCs. Also it is shown that class AB SI ADCs occupy less die area than SC ADCs for a given resolution. © 2007 IEEE  

In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW  

This paper proposes an Age-Dependent Clustering (ADC) structure to be used for prognostics. To achieve this aim, a step-by-step methodology is introduced, that includes clustering, reproduction, mapping, and finally estimation of Remaining Useful Life (RUL). In the mapping step, a neural fitting tool is used. To clarify the age-based clustering concept, the main elements of the ADC model is discussed. A Genetic algorithm (GA) is used to find the elements of the optimal model. Lastly, the fuzzy technique is applied to modify the clustering. By investigating a case study on the health monitoring of some turbofan engines, the efficacy of the proposed method is demonstrated. The results showed... 

Most existing methods for satellite attitude control assume that full knowledge of satellite attitude is available by algebraic manipulation of at least two vector measurements from attitude sensors such as Sun, Earth-horizon, Earth-magnetic or star tracker sensors. Kalman filtering is usually used when only one vector measurement is available, however, asymptotic stability of nonlinear and uncertain dynamics of satellite is not guaranteed in this case. This technical note presents a coupled nonlinear estimator-controller for satellite attitude determination and control by using a 3-axis gyro and a single vector measurement for a fully actuated satellite. We assume that the moment-of-inertia... 

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-Amplifier stage) is limited to V dd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above V dd=2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster... 

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

A low-power technique for high-resolution comparators is introduced. In this technique, p-type metal-oxide-semiconductor field-effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter-based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n-channel metal-oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power...