Sharif Digital Repository

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit... 

A novel two-level signaling technique in OOC-based fiber-optic CDMA systems is proposed. Users of the system are categorized into two classes. Users of class 1 and 2 transmit the optical pulses at power level P and 2P respectively. We study two kinds of receiver structure for the proposed two-level system. For the first structure we use ordinary AND logic gate and for the second one we use optical ADC with AND logic gate structure. We obtain the system performance and we show that for the two-level signaling multi-access interference is considerably suppressed. Two-level signaling increase system performance and capacity and also presents different QoS for the users in two classes. © 2009... 

Most existing methods for satellite attitude control assume that full knowledge of satellite attitude is available by algebraic manipulation of at least two vector measurements from attitude sensors such as Sun, Earth-horizon, Earth-magnetic or star tracker sensors. Kalman filtering is usually used when only one vector measurement is available, however, asymptotic stability of nonlinear and uncertain dynamics of satellite is not guaranteed in this case. This technical note presents a coupled nonlinear estimator-controller for satellite attitude determination and control by using a 3-axis gyro and a single vector measurement for a fully actuated satellite. We assume that the moment-of-inertia... 

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel... 

In this paper a theoretical comparison between the performance of switched-capacitor (SC) and switched-current (SI) pipeline analog-to-digital converters (ADCs) is presented. Power dissipation and die area of SC and SI implementations are compared based on linearity and noise constraints. It is shown that if nonlinearity errors of the class AB SI ADCs are removed by calibration, their performance prevails that of the SC ADCs. Also it is shown that class AB SI ADCs occupy less die area than SC ADCs for a given resolution. © 2007 IEEE  

This paper proposes an Age-Dependent Clustering (ADC) structure to be used for prognostics. To achieve this aim, a step-by-step methodology is introduced, that includes clustering, reproduction, mapping, and finally estimation of Remaining Useful Life (RUL). In the mapping step, a neural fitting tool is used. To clarify the age-based clustering concept, the main elements of the ADC model is discussed. A Genetic algorithm (GA) is used to find the elements of the optimal model. Lastly, the fuzzy technique is applied to modify the clustering. By investigating a case study on the health monitoring of some turbofan engines, the efficacy of the proposed method is demonstrated. The results showed... 

In this paper, an optimal down sampler is used for Associate Discrete Circuit (ADC) based modeling and simulation of basic switching converters. Characteristic equation of backward Euler based discrete model of the circuit is used to find the value for down sampling. Using ADC modeling, fixed admittance matrix can be achieved for modeling switching converters and using down sampler, additional switch and diode current oscillations are minimized. Real-time digital simulation of buck converter using ADC with down sampler method is implemented on a Field Programmable Gate Array (FPGA) and the results are those expected without additional numerical oscillations. Based on the place-and-route... 

Signal to Noise and Distortion Ratio (SNDR) is widely chosen for dynamic characterization of ADC. For pipelined ADC in which the inner circuits' errors accumulate at the output, analysis of the origins of SNDR and its characterization can be very hard. However, due to a relationship between maximum INL of ADC and the distortion in its output codes, SNDR can be derived as a function of maximum INL value and its position in output codes. Utilizing this relationship, this paper develops two methods for SNDR enhancement that do not cost much power. The 50k sampled Monte-Carlo simulation in the behavioral level indicates 75% increase in the possibility of having SNDR > 60db just by utilizing... 

Based on MRI diffusion and perfusion, a new criterion for detection and the healing progress of damaged tissue is suggested. The study is based on the ratio of capillary radii in symmetrical damaged and normal tissue neighboring spaces. The Apparent Diffusion Coefficient (ADC) and Cerebral Blood Flow (CBF) were measured in the brain tissues of six male Wistar rats utilizing suggested MRI measurement techniques. The ADC values of damaged and normal regions were (392 ± 34.1) × 10-6 mm2s-1 and (659 ± 40.7) × 10-6 mm2s-1, respectively. The CBF values of damaged and normal regions were 14.5 ± 10.13 ml/min/ 100 g and 125 ± 41.03 ml/min/100 g, respectively. The geometrical parameters of the... 

In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

Computationally exhaustive time-domain Monte Carlo (MC) simulations are commonly conducted to obtain the static characteristics of a residual analog-to-digital converter (ADC) (e.g., pipelined ADC) for the calculation of the integral nonlinearity (INL) and differential nonlinearity (DNL). In this brief, a new ultrahigh-speed, yet precise, behavioral-level dc characterization algorithm for residual-based ADC is introduced. The algorithm derives the transition points of a given stage of the ADC based on the random parameters of that stage. Then, it merges the dc characteristics of all stages together to extract detailed dc input-output characteristics for the entire ADC. Then, the exact amount... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

In theory, diffusion and perfusion information in MRI maps can be combined to yield morphological information, such as capillary density, volume and possibly capillary plasma velocity. This paper suggests a new method for determination of mean radius, length and capillary density in normal regions using diffusion and perfusion MRI. Mean Transit Time (MTT), Cerebral Blood Volume (CBV), Apparent Diffusion Coefficient (ADC), pseudo-diffusion coefficient (D*) and ΔR2 and ΔR2* values were utilized to calculate mean radius, length and capillary density. To verify the proposed theory, a special protocol was designed and tested on normal regions of a male Wistar rat using obtained functions. Mean... 

Bi-directional RSFQ benefits from using both positive and negative SFQ pulses to manipulate and transfer digital data. This allows more flexibility in the design of simpler circuits with enhanced performance. On the other hand, using the AC bias current, one can replace on-chip resistive current distributors with inductors. This resembles RQL logic, but in contrast to RQL, it is possible to use the well-established standard RSFQ cells in bi-directional RSFQ. These two advantages (energy-efficient computation and flexibility in design) make bi-directional RSFQ a powerful tool in next-generation supercomputers and also compatible with ultra-low-temperature quantum computers. In this work, to... 

This paper presents a methodology for implementing of the mathematical model of H-Bridge converter in an FPGA-based Real-Time simulator. Furthermore, it introduces a new method for choosing parameters of the Associate Discrete Circuit (ADC) model of semiconductor switches. The ADC-based model allows obtaining a fixed topology irrespective of switches states for the power electronic converters in the digital simulation. Backward-Euler based discretized state space matrix (SSM) of the circuit used for ADC parameter. Choosing appropriate switch parameter is based on 1) reducing the distance of SSM eigenvalues from origin in z-Plane to reduce settling-Time of system response; and 2) reducing the... 

In this paper, a modified frequency control model is proposed, where the demand response (DR) control loop is added to the traditional load frequency control (LFC) model to improve the frequency regulation of the power system. One of the main obstacles for using DR in the frequency regulation is communication delay which exists in transferring data from control center to appliances. To overcome this issue, an adaptive delay compensator (ADC) is used in order to compensate the communication delay in the control loop. In this regard, a weighted combination of several vertex compensators, whose weights are updated according to the measured delay, is employed. Generating the phase lead is the...