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A two-stage pipelined passive charge-sharing SAR ADC

Imani, A ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/APCCAS.2008.4745980
  3. Publisher: 2008
  4. Abstract:
  5. This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18um CMOS process, the 12-bits, 40MS/sec ADC core consumes 7mW from a 1.8V supply
  6. Keywords:
  7. Charge sharing ; CMOS process ; Inherent limitations ; Low-power ; Pipeline architectures ; Proposed architectures ; SAR ADC ; Two stages ; Pipelines ; Synthetic apertures ; Multicarrier modulation
  8. Source: APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; January , 2008 , Pages 141-144 ; 9781424423422 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4745980