Sharif Digital Repository

In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure  

The interest in action and gesture recognition has grown considerably in the last years. In this paper, we present a survey on current deep learning methodologies for action and gesture recognition in image sequences. We introduce a taxonomy that summarizes important aspects of deep learning for approaching both tasks. We review the details of the proposed architectures, fusion strategies, main datasets, and competitions. We summarize and discuss the main works proposed so far with particular interest on how they treat the temporal dimension of data, discussing their main features and identify opportunities and challenges for future research. © 2017 IEEE  

New advances in mobile-computer technology, together with the advent of wireless networking, introduce new requirements, capabilities and concerns to the computer science and industry. In this paper, we discuss the special requirements of file sharing in mobile environments. Then our proposed architecture for mobile file sharing (MobFish) is presented. Finally, we present an implementation of the proposed architecture based on its special design tactics. © 2006 by Knowledge Systems Institute Graduate School. All rights reserved  

An efficient low-complexity VLSI architecture for timing synchronization of a real-time intensity modulation direct detection optical OFDM (IMDD-OOFDM) system is proposed, which results in a significant area reduction. This architecture calculates the correlation among cyclic prefix (CP) regions to estimate the beginning of the OFDM symbol. The proposed architecture utilizes only one functional unit for this purpose, while the throughput is devised for high data-rate optical OFDM systems. Synthesis results of this architecture proves an area saving of 31% compared to the previous work. Moreover, the performance of the correlation method is significantly improved due to a modification applied... 

We propose an all-optical arbitration architecture to resolve end-point contention in the optical networks-on-chip. The proposed architecture reduces on-chip optical power and energy losses by 37% and 21%, respectively, compared to Corona's token-based control plane  

Cryptographic computation exploits finite field arithmetic and, in particular, multiplication. Lightweight and fast implementations of such arithmetic are necessary for many sensitive applications. This brief proposed a low-complexity systolic Montgomery multiplication over GF(2m). Our complexity analysis shows that the area complexity of the proposed architecture is reduced compared with the previous work. This has also been confirmed through our application-specific integrated circuit area and time equivalent estimations and implementations. Hence, the proposed architecture appears to be very well suited for high-throughput low-complexity cryptographic applications  

Automatic image annotation (AIA) is an image retrieval mechanism to extract relative semantic tags from visual content. So far, the improvement of accuracy in newly developed such methods have been about 1 or 2% in the F1-score and the architectures seem to have room for improvement. Therefore, the authors designed a more detailed architecture for AIA and suggested new algorithms for its main parts. The proposed architecture has three main parts: feature extraction, learning, and annotation. They designed a novel learning method using machine learning and probability bases. In the annotation part, they suggest a novel method that gains the maximum benefit from the learning part. The... 

This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18um CMOS process, the 12-bits, 40MS/sec ADC core consumes 7mW from a 1.8V supply  

The Time Modulated Array (TMA) provides multiple radiation beams at different frequencies, by turning the radiating elements on and off. In this paper, we propose to add polarization diversity to a wireless communication link by leveraging the capabilities of the TMA. The proposed architecture switches between two orthogonal polarizations, instead of turning the antenna off, providing polarization diversity for the receivers. We show that the beams of each polarization at the sidebandsare exactly the same. However, the switching sequence should be optimized for the fundamental frequency to provide the same radiation level at each sideband. Two different switching sequences are proposed,... 

Cache memories constitute a large fraction of processor chip area and are highly vulnerable to soft errors caused by energetic particles. To protect these memories, most of the modern processors employ Error Detection Codes (EDCs) or Error Correction Codes (ECCs). EDCs/ECCs impose significant overheads in terms of area and energy; these overheads increase as a function of interleaving EDCs/ECCs to detect/correct multiple errors. This paper proposes a new cache architecture to minimize the area and energy overheads of EDCs/ECCs in set-associative L1-caches. Simulation results for a 4-way set-associative cache show that the proposed architecture reduces both the area and static power overheads... 

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

Promising advantages offered by resistive NonVolatile Memories (NVMs) have brought great attention to replace existing volatile memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in Field-Programmable Gate Arrays (FPGAs). One major limitation of employing NVMs in FPGAs is significant power and area overheads imposed by the Peripheral Circuitry (PC) of NVM configuration bits. In this paper, we investigate the applicability of different NVM technologies for configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). The proposed PCM-based architecture has been... 

Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design... 

Despite widespread use of SRAM-based reconfigurable devices (SRDs) in mainstream applications, their usage has been very limited in enterprise and safety-critical applications due to SRAM susceptibility to soft errors. Previous mitigation techniques to protect SRDs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to multiple bit upsets (MBUs). In this paper, we present a highly available fault-tolerant architecture to protect SRD-based designs against MBUs in both configuration and user bits. In the proposed architecture, the entire design is duplicated with respect to the relative locations of logic blocks within the SRD and... 

High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable... 

Nowadays, deployment of peer-to-peer video streaming systems over wireless mesh networks has attained raising popularity among large number of users around the world. In this paper, we present an efficient peer-to-peer live video streaming architecture over multi-hop wireless mesh networks. In our proposed architecture, we take the physical topology of network into account and based on a distributed distributed locality-aware neighbor selection algorithm in the overlay construction phase, we generate an efficient mesh-based overlay on top of wireless mesh networks. In locality-aware neighbor selection algorithm, instead of choosing randomly, peers find their best neighbors based on their... 

This paper proposes a nanophotonic Network-on-Chip architecture based on the traditional Cube-Connected Cycles topology (CCC), which is named as ONC3. We also suggest a contention-free quasi-Dimension-Order-Routing algorithm for the proposed structure. Compared to the previous 2D layouts, our novel scheme lessens the crosstalk parameter of the insertion loss and consequently, the power consumption. Besides, the router structure is area-efficient. On the other hand, optical destination checking supersedes electrical resource reservation, with utilizing passive wavelength routing method and Wavelength Division Multiplexing scheme, simultaneously. The efficiency of the proposed architecture, in... 

A pipelined architecture is developed for a Sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The promising feature of the proposed SMC receiver is achieving the near-bound performance in fading channels without using any decision feedback, training or pilot symbols. The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks, i.e., the SMC core, weight calculator, and resampler. Hardware efficient/parallel architectures for each functional block including the resampling block is developed. The novel feature of the proposed architecture is that makes the execution time of the resampling independent... 

In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA... 

We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and...