Sharif Digital Repository

Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations.... 

High resolution and low power analog to digital converters are used in wireless communication receivers, Sensor Networks and Medical Instrumentations. Reducing power consumption at a high conversion rate is one of the most basic challenges for these converters. Pipelined SAR structure is considered for 40-50 MS/s and 10-12 bits, and is of interest because of consuming low power and using a small area. Besides using Pipelined SAR structure, circuit level and system level modifications are also proposed to decrease the power consumption. The ADC is designed in 0.18µm CMOS technology with 1.2v supply voltage. The results show 4.5mW power consumption, when ENOB is 11.04bit, which is very low... 

High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 40 M sample/s with a power consumption of 20mW for the input level of 1Vp-p and a 1V power supply in 0.13μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized analytically which leads to simple back-envelope formulas to... 

High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to... 

The digital nature of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) suits them for the new technologies with small gate length and low power applications. Applications such as ultra-wideband receivers, satellite receivers and high speed serial links demand medium resolution and high sampling rate ADCs. Due to binary search algorithm speed limitations, SAR ADCs belong to low to moderate speed category. In this thesis time-interleaving and two-bit-per-cycle technique are used in order to increase SAR ADC sampling rate. These techniques are both sensitive to offset and if the comparators used in SAR ADC have different offsets signal-to-noise-and-distortion will be... 

The successive approximation digital to analog converters are appropriate selection for use in new technologies and low-powered applications. Despite the low power consumption of this kind of converters, there are some applications like medical which require very low power consumption. In order to reduce the power consumption of SAR ADC, capacitive digital to analog converters and comparators are great importance. In this Thesis, monotonic switching method has been used, the switching power of this method is lower than the conventional method by 81.2%. Since the common mode of the output of this type of switch is variable, the offset is sensitive and requires a technique to resolve this... 

ADC is one of the key functional blocks of any mixed signal system and therefore must be optimally designed concerning power, performance, resolution and silicon area. Among different architectures have been employed up to now, successive approximation register ADCs are known as the ones with lower power, more simplicity and lower sampling rate. Benefiting from scaling down the CMOS technology results in higher sampling rate and lower power SAR ADCs replacing other types of ADCs. To achieve the desired ADC performance, efforts are usually focused on the improvement of circuit techniques as well as on the introduction of new or combinational architectures based on SAR ADCs. This thesis aims... 

Massive MIMO is a key enabling technology in the fifth generation (5G) wireless communication systems. In this technology, the base station is equipped with a large number of antennas (e.g. 100-200) and communicates with a relatively smaller number of user terminals. The large number of antennas at the base station, on one hand, has enabled unprecedented improvements in data rate and energy-efficiency, while on the other hand has posed challenges on the practical deployment of this technology.One of these challenges, is the high computational complexity of the baseband processing algorithms, such as precoding, due to the large number of antennas. In this research, we propose a novel ZF... 

Nowadays, increasingly improvements in the digital technology and the advantages of using digital signal processing methods lead engineers to use digital signal processing instead of analog processing in variant domains. However, speed limitations in analog to digital converters (ADCs) and data transfer ports prevent its penetration to high frequency signals region. In this thesis, an Instantaneous Frequency Measurement (IFM) system that can measure frequency in the range of 2-18 GHz is implemented fully digital (DIFM) on FPGA. To do so, monobit sampling technique with the sampling rate of 10 GHz is selected, and GTX high speed serial port is configured to transfer digital data into FPGA.... 

Increasing demand for digital systems has led to developing signal processing in the digital domain. For this purpose, Analog to Digital Converters is used to convert analog signals to digital ones. Apart from that, by decreasing the size of transistors, it has been possible to implement the system on a chip that needs communication between analog and digital signals. The designed converter in this project is suitable for instrumentation purposes and especially for use in the control loop of a DC­DC digitally voltage converter. ADC architectures are mainly classified into two groups attributed with high bandwidth or with high resolution. Nature of on­chip measurement requires high... 

In many industries, including oil and gas industries, power plants, refineries, petrochemicals, steel and cement industries, industrial complexes and consumer industries, there are tanks for storing materials. It is necessary to measure level of products while they are stored in tanks of different sizes. Ultrasonic is one of the non-contact and accurate measurement technologies that can provide a suitable solution for liquid tank monitoring. The purpose of this thesis is to design and build the electronic parts (transmitter and receiver circuits) of an ultrasonic system that is capable of detecting levels at a distance of less than 5 meters with an accuracy of 0.5 % full scale. In this... 

Phase noise is one of the important parameters in telecommunication systems and its measurement has always been considered. Digital phase noise measurement methods have a simpler implementation and calibration than analog types. Also, in digital methods, amplitude noise and phase noise can be separated and measured both at the same time. Comparing the phase noise of two oscillators with different frequencies is another major advantage of digital methods. The sensitivity of digital methods is limited to the noise of their analog-to-digital converters. Cross-correlation technique is used to reduce the minimum measurable level of phase noise. This method reduces the internal noise of the... 

One of the applications of signal digitization is its use in nuclear spectroscopy and in particular gamma ray spectroscopy. Parameters such as pulse amplitude and formation, pulse shrinkage correction or reduction, and pulse sampling are performed by the amplifier circuit and MCA. Such algorithms have advantages such as real-time pulse height analysis, high flexibility and significant cost reduction.Therefore, in this project, an attempt has been made to design a pulse analyzer system using electronic circuits and a computer ADC sound card. Optimal system will detect, amplify and shape the detector input signal, reduce the effect of pulse accumulation, count the number of pulses, and so... 

Sigma-delta modulators have largely been implemented as discrete-time (DT) circuits because of their low sensitivity to circuit nonidealities, and their frequency scaling specification, however a continuous-time (CT) design offers significant advantage in the design of high accuracy, high speed analog to digital converters (ADC). A CT design allows for relaxed amplifier(s) bandwidth and power requirements, which enables the realization of high accuracy modulators with bandwidths of several megahertz at low power consumption. Furthermore CT modulators provide inherent anti-aliasing filtering which becomes especially important at low oversampling ratios. This thesis reports the design of a... 

Delta-Sigma Analog-to-Digital converters have been positioned themselves as robust reliable converters so far. The magic Of extracting high resolutions from low bit ADC has made them popular between designers. Previously, the noise-shaping magic was used in high-resolution applications such as high-quality audio signal converters. However, as the technology scales and proceeds, these converters are approaching RF applications, too. Power and OSR trade-off limits this progress. To increase OSR in bandpass delta-sigma modulators, more power should be consumed to increase the quality factor of loop filters. In this thesis, a systematic approach has been utilized. An n-path filter is employed... 

Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog... 

With the rapid development of wireless communication standards, the co-existence of multiple standards in a single chip becomes inevitable. It is also fueling interest in analog to digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions with adaptive power consumption. Employing such ADCs rather than using multiple individually power-optimized ADCs results in a great reduction of silicon area. Hence, a reconfigurable ADC can reduce time to market, and save costs.
This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The... 

High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a... 

Considering the drastical increasing of greenhouse gases in the atmosphere, especially carbon dioxide, reduction of these gases seems necessary to combat global warming. Fossil fuel power plants are one of the main sources of CO2 emission. In this thesis, CO2 capture from a natural gas fired combined cycle power plant using different oxygen percent in air feed is studied. Aspen Plus was used to evaluate the effect of this capture technology on the plant efficiency and energetic parameters of the system. Aspen Hysys is used to simulate Amine absorption tower and Air Separation cryogenic tower. Since the oxygen production plant, CO2 capture and transport are cost and energy intensive, the cost... 

SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...