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High-Speed Low-Power 10-bit Pipeline Analog to Digital Converter

Hashemi, Mohsen | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 41470 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharif Khani, Mohammad; Atarodi, Mojtaba
  7. Abstract:
  8. High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 40 M sample/s with a power consumption of 20mW for the input level of 1Vp-p and a 1V power supply in 0.13μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In addition, a new low-voltage architecture for dynamic comparators is proposed. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum sizes of sampling and feedback capacitors, stage resolution, tail current and opamp transistor sizes. The pipeline converter was implemented in Cadence software environment by using the parameter values derived in MATLAB software as initial values. Next the desired design criteria were obtained by adjusting the parameters through try and error. The final design is a 10 bit analog to digital converter with a power consumption of 4.1 mw and SNDR = 56.2 dB for the input rate of Fin = 1 MHz , ENOB = 9.04 , INL < 1 LSB and DNL < 0.7 LSB.
  9. Keywords:
  10. Analog to Digital Converter ; Low Power System ; Optimization ; Pipeline Converter ; High Speed Data Converter

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