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Low-Power Reconfigurable Pipeline ADC for Multi-Standard Communication

Esmaeelzadeh, Hani | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44485 (05)
  4. University: Sharif University Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifkhani, Mohammad; Shoaee, Omid
  7. Abstract:
  8. With the rapid development of wireless communication standards, the co-existence of multiple standards in a single chip becomes inevitable. It is also fueling interest in analog to digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions with adaptive power consumption. Employing such ADCs rather than using multiple individually power-optimized ADCs results in a great reduction of silicon area. Hence, a reconfigurable ADC can reduce time to market, and save costs.
    This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The re-configurability on resolution is achieved by changing the stage resolution rather than omitting the stages. Thus, stages with higher resolutions can be employed as first stages in a pipeline chain, which significantly reduces the power consumption in high resolution modes. It is also illustrated that for applications in which a wide range of resolution is demanded a Hybrid method can be employed. In this method, a combination of the proposed and traditional methods is adopted to yield higher power efficiency.
    To verify the proposed method, a reconfigurable pipeline ADC with 6 different modes which changes the resolution between 10, 11 and 12 bits and the sampling rate between 10-to-80 MS/s, is designed and simulated in 90-nm CMOS technology which utilizes a 1.2V supply voltage. This ADC can be targeted for a variety of communication standards such as WiFi, LTE, Wimax, and WCDMA. To compare the performance of reconfigurable ADCs, a new FOM which is the RMS of different modes’ FOM is defined. The achieved effective FOM of the designed ADC is 0.235 pJ/Conv-step
  9. Keywords:
  10. Analog to Digital Converter ; Pipeline Converter ; Low Power System ; Reconfigurable Converter ; Communication Standards

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