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WIPE: wearout informed pattern elimination to improve the endurance of NVM-based caches

Asadi, S ; Sharif University of Technology | 2017

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  1. Type of Document: Article
  2. DOI: 10.1109/ASPDAC.2017.7858318
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2017
  4. Abstract:
  5. With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing the activity of frequent data patterns. Simulation results show that WIPE improves the endurance by up to 93% with negligible overheads. © 2017 IEEE
  6. Keywords:
  7. Endurance ; Frequent data pattern ; Computer aided design ; Data storage equipment ; Digital storage ; Durability ; Nonvolatile storage ; Static random access storage ; Cache ; Data manipulations ; Data patterns ; Non-volatile memory ; Non-volatile memory technology ; On-chip cache ; Online coding ; Wearout ; Cache memory
  8. Source: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 16 January 2017 through 19 January 2017 ; 2017 , Pages 188-193 ; 9781509015580 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/7858318/authors#authors