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    Beamforming, null-steering, and simultaneous spatial and frequency domain filtering in integrated phased array systems

    , Article AEU - International Journal of Electronics and Communications ; Volume 110 , 2019 ; 14348411 (ISSN) Karami, P ; Atarodi, S. M ; Sharif University of Technology
    Elsevier GmbH  2019
    Abstract
    In the case that phased array systems are not capable of attenuating interferences, Radio Frequency (RF) front-ends and Analog Digital Converters (ADCs) with a large dynamic range are required to avoid saturation of the receiver. This leads to a higher power consumption. In this paper, employing N-path circuits in Mixer-First receivers, a novel method is introduced in which spatial and frequency blockers are eliminated right before entering the system on the antennas input. In fact using this technique, adjustable spatial notch filter and band-pass frequency filter are implemented to suppress spatial and frequency interferences. The proposed method enhances the robustness and effectiveness... 

    High Speed Digital Receiver, Design and Implementation

    , M.Sc. Thesis Sharif University of Technology Aarabi, Masoud (Author) ; Sanaei, Esmaeel (Supervisor) ; Pezeshk, Amir Mansoor (Supervisor)
    Abstract
    Nowadays, increasingly improvements in the digital technology and the advantages of using digital signal processing methods lead engineers to use digital signal processing instead of analog processing in variant domains. However, speed limitations in analog to digital converters (ADCs) and data transfer ports prevent its penetration to high frequency signals region. In this thesis, an Instantaneous Frequency Measurement (IFM) system that can measure frequency in the range of 2-18 GHz is implemented fully digital (DIFM) on FPGA. To do so, monobit sampling technique with the sampling rate of 10 GHz is selected, and GTX high speed serial port is configured to transfer digital data into FPGA.... 

    10-Bit 500-MS/s Pipelined Analog to Digital Converter

    , M.Sc. Thesis Sharif University of Technology Noormohammadi Khyarak, Mehdi (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to... 

    Deign of 10 Bit 200 MS/s Pipeline Analog to Digital Converter in 0.18 um

    , M.Sc. Thesis Sharif University of Technology Ghaed Rahmati, Hanie (Author) ; Haj Sadeghi, Khosro (Supervisor)
    Abstract
    High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
    To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a... 

    Circuit & Systematic Design of Low Power & High Speed SAR ADC

    , M.Sc. Thesis Sharif University of Technology Khorami, Ata (Author) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
    The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a... 

    Circuit and Systematic Design of Low Power SAR ADC

    , M.Sc. Thesis Sharif University of Technology Yazdani, Behnam (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog... 

    Design and Implementation of a Low Power High Speed ADC Based on SAR ADC

    , M.Sc. Thesis Sharif University of Technology Fazel, Ziba (Author) ; Atarodi, Mojtaba (Supervisor) ; Saeedi, Saeed (Co-Advisor)
    Abstract
    ADC is one of the key functional blocks of any mixed signal system and therefore must be optimally designed concerning power, performance, resolution and silicon area. Among different architectures have been employed up to now, successive approximation register ADCs are known as the ones with lower power, more simplicity and lower sampling rate. Benefiting from scaling down the CMOS technology results in higher sampling rate and lower power SAR ADCs replacing other types of ADCs. To achieve the desired ADC performance, efforts are usually focused on the improvement of circuit techniques as well as on the introduction of new or combinational architectures based on SAR ADCs. This thesis aims... 

    Time to Digital Converters for ADPLL Applications

    , Ph.D. Dissertation Sharif University of Technology Molaei, Hasan (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations.... 

    Design and Implenentation of a Bandpass Delta-sigma Modulator Using High-Q N-path Filter

    , M.Sc. Thesis Sharif University of Technology Kabiri, Mohammad Reza (Author) ; Atarodi,Mojtaba (Supervisor) ; Sharifkhani, Mohammad (Co-Supervisor)
    Abstract
    Delta-Sigma Analog-to-Digital converters have been positioned themselves as robust reliable converters so far. The magic Of extracting high resolutions from low bit ADC has made them popular between designers. Previously, the noise-shaping magic was used in high-resolution applications such as high-quality audio signal converters. However, as the technology scales and proceeds, these converters are approaching RF applications, too. Power and OSR trade-off limits this progress. To increase OSR in bandpass delta-sigma modulators, more power should be consumed to increase the quality factor of loop filters. In this thesis, a systematic approach has been utilized. An n-path filter is employed... 

    Design of a High Speed Time-Interleaved SAR ADC

    , M.Sc. Thesis Sharif University of Technology Ghajari, Shahaboddin (Author) ; Sharifkhani, Mohammad (Supervisor) ; Fotowat Ahmadi, Ali (Supervisor)
    Abstract
    The digital nature of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) suits them for the new technologies with small gate length and low power applications. Applications such as ultra-wideband receivers, satellite receivers and high speed serial links demand medium resolution and high sampling rate ADCs. Due to binary search algorithm speed limitations, SAR ADCs belong to low to moderate speed category. In this thesis time-interleaving and two-bit-per-cycle technique are used in order to increase SAR ADC sampling rate. These techniques are both sensitive to offset and if the comparators used in SAR ADC have different offsets signal-to-noise-and-distortion will be... 

    Iterative Methods for Sparse Reconstruction in Level Crossing Analog to Digital Converters

    , Ph.D. Dissertation Sharif University of Technology Boloursaz Mashhadi, Mahdi (Author) ; Marvasti, Farokh (Supervisor)
    Abstract
    In this research, we propose analog to digital (A/D) converters based on Level Crossing (LC) sampling and the corresponding signal processing techniques for effecient acquisition of spectrum-sparse signals. Spectrum-sparse signals arise in many applications such as cognitive radio networks, frequency hopping communications, radar/sonar imaging systems, musical audio signals and many more. In such cases, the signal components maybe sparsely spread over a wide spectrum and need to be acquired at a reasonable cost without prior knowledge of their frequencies. Compared with the literature, the proposed scheme not only enables efficient acquisition of spectrum-sparse signals with a less complex... 

    Design and Fabrication of Ultrasonic Level-meter System

    , M.Sc. Thesis Sharif University of Technology Tavoosi, Ali (Author) ; Nejat Pishkenari, Hossein (Supervisor) ; Salarieh, Hassan (Co-Supervisor)
    Abstract
    In many industries, including oil and gas industries, power plants, refineries, petrochemicals, steel and cement industries, industrial complexes and consumer industries, there are tanks for storing materials. It is necessary to measure level of products while they are stored in tanks of different sizes. Ultrasonic is one of the non-contact and accurate measurement technologies that can provide a suitable solution for liquid tank monitoring. The purpose of this thesis is to design and build the electronic parts (transmitter and receiver circuits) of an ultrasonic system that is capable of detecting levels at a distance of less than 5 meters with an accuracy of 0.5 % full scale. In this... 

    A low-power low-offset dynamic comparator for analog to digital converters

    , Article Microelectronics Journal ; Vol. 45, issue. 2 , February , 2014 , pp. 256-262 ; ISSN: 00262692 Hassanpourghadi, M ; Zamani, M ; Sharifkhani, M ; Sharif University of Technology
    Abstract
    A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with... 

    A sigma-delta analog to digital converter based on iterative algorithm

    , Article Eurasip Journal on Advances in Signal Processing ; Volume 2012, Issue 1 , 2012 ; 16876172 (ISSN) Kafashan, M ; Ghorbani, M ; Marvasti, F ; Sharif University of Technology
    2012
    Abstract
    In this article, we present a new iterative algorithm aimed at improving the performance of the sigma-delta analog to digital (A/D) converter. We subject the existing sigma-delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma-delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to... 

    Non-uniform sampling based on an adaptive level-crossing scheme

    , Article IET Signal Processing ; Volume 9, Issue 6 , 2015 , Pages 484-490 ; 17519675 (ISSN) Malmirchegini, M ; Kafashan, M. M ; Ghassemian, M ; Marvasti, F ; Sharif University of Technology
    Institution of Engineering and Technology  2015
    Abstract
    Level-crossing (LC) analog-to-digital (A/D) converters can efficiently sample certain classes of signals. An LC A/D converter is a real-time asynchronous system, which encodes the information of an analog signal into a sequence of nonuniformly spaced time instants. In particular, this class of A/D converters uses an asynchronous data conversion approach, which is a power efficient technique. In this study, the authors propose adaptive and multi-level adaptive LC sampling models as alternatives to conventional LC schemes and apply an iterative algorithm to improve the reconstruction quality of LC A/D converters. This simulation results show that multi-level adaptive LC outperforms... 

    A high energy-efficiency and low-area switching scheme for SAR ADCs

    , Article Analog Integrated Circuits and Signal Processing ; 18 November , 2020 Momeni, M ; Sharifkhani, M ; Yazdani, S. B ; Sharif University of Technology
    Springer  2020
    Abstract
    A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

    Performance improvement of level-crossing A/D converters

    , Article 2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications, ICT-MICC 2007, Penang, 14 May 2007 through 17 May 2007 ; February , 2007 , Pages 438-441 ; 1424410940 (ISBN); 9781424410941 (ISBN) Malmir Chegini, M ; Marvasti, F ; Sharif University of Technology
    2007
    Abstract
    Level Crossing (LC) Analog-to-Digital converters have been suggested as an asynchronous alternative to conventional schemes. It is our intention to improve the performance of these LC converters. In this paper, we also suggest alternative adaptive and multi-level adaptive LC schemes and use an iterative method to drastically improve the performance of LC converters. The impressive improvement of these schemes make LC converters a potential competitor to other conventional A/D converters such as Sigma Delta Modulators (SDM). ©2007 IEEE  

    INL prediction method in pipeline ADCs

    , Article APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 4 December 2006 through 6 December 2006 ; 2006 , Pages 13-16 ; 1424403871 (ISBN); 9781424403875 (ISBN) Nikandish, G ; Sedighi, B ; Bakhtiar, M. S ; Sharif University of Technology
    2006
    Abstract
    In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

    A high energy-efficiency and low-area switching scheme for SAR ADCs

    , Article Analog Integrated Circuits and Signal Processing ; Volume 106, Issue 2 , 2021 , Pages 449-457 ; 09251030 (ISSN) Momeni, M ; Sharifkhani, M ; Yazdani, S. B ; Sharif University of Technology
    Springer  2021
    Abstract
    A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

    Energy/Throughput Efficient Signalings for Optical CDMA Systems

    , Ph.D. Dissertation Sharif University of Technology Ghaffari, Babak (Author) ; Salehi, Javad (Supervisor)
    Abstract
    A major breakthorugh in all-optical wireless and wired communication networks is taking place in the last mile such as access networks. In this case، study-ing various multiple-access techniques in all-optical domain، especially optical code-division multiple-access (OCDMA) technique is of utmost importance. In this thesis we study several key signalings and modulation techniques in the con-text of their performance، energy and throughput efficiency for OCDMA systems. In particular we introduce novel multilevel signaling techniques for OOC-based fiber-optic CDMA systems and present their corresponding all-optical receiver structures using advanced optical devices such as optical-logic-gate...