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Analysis and design of a DC to 18 GHz 6-bit attenuator with simultaneous phase and gain error correction

Ahmadikia, A ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1016/j.aeue.2019.152829
  3. Publisher: Elsevier GmbH , 2019
  4. Abstract:
  5. In this paper the design of a digital step attenuator with simultaneous low phase and gain error characteristics is investigated. First, the loading effect of the consecutive blocks of an N-bit attenuator on the precision of the attenuation levels is analyzed. Then a modified structure to decrease the loading effect as well as the phase error of the attenuator blocks is presented. A comprehensive analysis of the circuit is performed and some design guidelines have described. Finally, a 6-bit attenuator with attenuation range of 0.5–31.5 dB and resolution of 0.5 dB is implemented in 0.18 µm complementary metal–oxide-semiconductor (CMOS) technology. The root mean square (RMS) gain error and RMS phase error of the designed circuit for different process corners and DC to 18 GHz are below 0.59 dB and 4.2°, respectively. © 2019 Elsevier GmbH
  6. Keywords:
  7. Attenuator ; Digital step attenuator ; Loading effect ; RMS gain error ; RMS phase error ; CMOS integrated circuits ; Error correction ; Microwave measurement ; Oxide semiconductors ; CMOS switch ; Digital step attenuators ; Gain errors ; Loading effects ; Phase error ; Electric attenuators
  8. Source: AEU - International Journal of Electronics and Communications ; Volume 110 , 2019 ; 14348411 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S1434841119309768