Loading...
Search for:
rms-phase-error
0.005 seconds
Analysis and design of a DC to 18 GHz 6-bit attenuator with simultaneous phase and gain error correction
, Article AEU - International Journal of Electronics and Communications ; Volume 110 , 2019 ; 14348411 (ISSN) ; Karami, P ; Atarodi, S. M ; Sharif University of Technology
Elsevier GmbH
2019
Abstract
In this paper the design of a digital step attenuator with simultaneous low phase and gain error characteristics is investigated. First, the loading effect of the consecutive blocks of an N-bit attenuator on the precision of the attenuation levels is analyzed. Then a modified structure to decrease the loading effect as well as the phase error of the attenuator blocks is presented. A comprehensive analysis of the circuit is performed and some design guidelines have described. Finally, a 6-bit attenuator with attenuation range of 0.5–31.5 dB and resolution of 0.5 dB is implemented in 0.18 µm complementary metal–oxide-semiconductor (CMOS) technology. The root mean square (RMS) gain error and...
An S-Band CMOS 6-Bit vector-sum phase shifter with low RMS phase error using frequency-to-voltage converter feedforward loop
, Article Journal of Circuits, Systems and Computers ; Volume 29, Issue 3 , 2020 ; Safarian, A ; Sharif University of Technology
World Scientific Publishing Co. Pte Ltd
2020
Abstract
In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2-4GHz) applications. The designed phase shifter in 180nm CMOS technology achieves an RMS phase error in the range of 0.607-1.18? with -50dBm input signal over 2-4GHz frequency band. With lower input signal of -75dBm, the RMS phase error is 0.621-1.34? for 2-4GHz input frequency. The proposed phase shifter shows an RMS amplitude error...
A 6-Bit CMOS phase shifter for S - Band
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 58, Issue 12 PART 1 , 2010 , Pages 3519-3526 ; 00189480 (ISSN) ; Azizi, M ; Kiani, M ; Medi, A ; Atarodi, M ; Sharif University of Technology
Abstract
A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications