Sharif Digital Repository

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed... 

To get a more accurate model for the simulation of single electron transistors (SETs), we propose a new macro-model that includes an electron tunneling time calculation. In our proposed model, we have modified the previous models and have applied some basic corrections to the formulas. In addition, we have added a switched capacitor circuit, as a quantizer, to calculate the electron tunneling time. We used HSPICE for a high-speed simulation and observed that the simulation results obtained from our model match more closely with that of SIMON 2.0. We also could evaluate the time of electron tunneling through the barrier by using the quantizer. Clearly, our macro-model gives more accurate... 

In this paper a new technique called switched-resistor is used as an alternative to switched-capacitor circuits in a low-voltage low-power high-speed A/D converter. Simulation results for an 8-bit 150MS/s pipeline ADC are presented. This converter consumes 20mW from a 1.8V supply and provides an ENOB of 7.5bit. © 2007 IEEE  

In this paper, an optimized topology for switched-capacitor (SC) multilevel inverter is proposed. The proposed topology, which is referred to as Optimized Switched-Capacitor Multilevel Inverter (OSC-MI), offers a boosted staircase voltage by using only one dc source and fewer switches count. Since each industrial load requires a specific power factor (PF), an optimal converter can be designated in a way that it both satisfies the required PF and employs fewer switches and gate drivers. Therefore, the main strategy of reducing switches count in the proposed topology is to design the converter according to the required PF value. In this paper, the theoretical analytics and comparison results... 

Drawing an accurate relationship between settling time and the power consumption of the amplifier is a challenging problem in Switch Capacitor circuits especially when it includes non-linear effects. In this paper, a new method for the estimation of this relationship including both non-linear settling as a result of slew-rate and small signal settling in the 3 rd order amplifier is proposed. The results show that the proposed settling time estimation is more accurate than other conventional methods when it is compared with the circuit level simulations. The proposed method has error smaller than 10% for the third order OpAmp in estimating settling error. This is about two times more accurate... 

In this paper a theoretical comparison between the performance of switched-capacitor (SC) and switched-current (SI) pipeline analog-to-digital converters (ADCs) is presented. Power dissipation and die area of SC and SI implementations are compared based on linearity and noise constraints. It is shown that if nonlinearity errors of the class AB SI ADCs are removed by calibration, their performance prevails that of the SC ADCs. Also it is shown that class AB SI ADCs occupy less die area than SC ADCs for a given resolution. © 2007 IEEE  

A new second order sigma delta modulator with the reduced number of op-amps, to decrease static power consumption and area, is presented for voice band applications such as codecs. This switched capacitor modulator uses reused capacitor technique to reduce the input thermal noise and circuit area. It improves the DR of modulator by almost 0.5 bit. The modulator shows 87 dB DR for voice band while consuming 125 μW from a 2.5 V supply. © 2003 IEEE  

To get a more accurate model for simulation of single electron transistors (SETs), we have proposed a new macromodel that includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition, we have added a switched capacitor circuit, as a quantizer, to calculate the electron tunneling time. We used HSPICE for high-speed simulation and observed that the simulation results obtained from our model matched more closely with that of SIMON 2.0. We also could evaluate the time of electron tunneling through the barrier by using the quantizer. Clearly, our macro-model gives more... 

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the... 

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

Thermal noise is one of the most important limiting factors on the performance of switched-capacitor (SC) circuit due to the aliasing effect of wide-band thermal noise. In this paper a new simple method for estimating the effect of thermal noise is presented. In the proposed technique only the discrete sampled noise is considered. HSPICE simulator and analytical analysis are used to estimate the sampled noise specification on each clock state. Next, using difference equations of the circuit, time domain simulation is done by MATLAB. Based on this method, a SC integrator is analyzed and results compared to the measured noise response  

Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

This paper proposes a new method to detect and classify all kinds of faults, capacitor switching, and load switching in a power system network based on wavelet transform and support vector machines (SVMs). In this regard, a sample of a power system is simulated via MATLAB/Simulink, and by reading the voltage of the point of common coupling and using the wavelet transform, the differences of the outputs of the wavelet transform are investigated. The SVM approach is employed to distinguish the type of the transient (capacitor switching, fault, and/or load switching) in use for the high level outputs of the wavelet transform. Similar to neural networks, this method, which is based on learning,... 

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

A novel class AB architecture for single stage multipath differential amplifier is presented. The proposed amplifier combines the flipped voltage follower(FVF) for differential input and the nonlinear current mirror for active load. Applying these techniques to telescopic-cascode amplifier increases the unity-gain bandwidth, the DC gain and the slew rate while the same power consumption as the conventional telescopic cascade is achieved  

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching... 

One of the major limitations of the multilevel converters is the voltage unbalance between different levels. The techniques to balance the voltage between the different levels normally involve voltage clamping or capacitor charge and discharge control. However, traditional Flying Capacitor Converter (FCC) may be quite limited by the voltage unbalance of flying-capacitors that is the most serious problem. This paper describes operating principles of a new softswitching seven-level converter topology based on FCC for self-voltage stabilization and balancing. By adding power electronic devices to the traditional FCC topology, the proposed topology regulates the DC bus voltage and balances the... 

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 n ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400-3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to...