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Structural evolution during mechanical milling of nanometric and micrometric Al2O3 reinforced Al matrix composites
, Article Materials Science and Engineering A ; Volume 428, Issue 1-2 , 2006 , Pages 159-168 ; 09215093 (ISSN) ; Simchi, A ; Reihani, S. M. S ; Sharif University of Technology
2006
Abstract
The morphological and microstructural changes during mechanical milling of Al powder mixed with 5 vol% nanoscaled alumina particles (35 nm) were studied. The milling was performed in a planetary ball mill under argon atmosphere for various times up to 24 h. The process was also conducted for Al and Al-5 vol% Al2O3 (1 μm) powders to explore the role of reinforcement nanoparticles on the mechanical milling stages. The results showed that the addition of hard particles accelerate the milling process, leading to faster work hardening rate and fracture of the aluminum matrix. Meanwhile, the structural evolution during mechanical milling of the microcomposite powder occurred faster than that of...
Effect of high energy ball milling on compressibility and sintering behavior of alumina nanoparticles
, Article Ceramics International ; Volume 38, Issue 4 , May , 2012 , Pages 2627-2632 ; 02728842 (ISSN) ; Aminzare, M ; Razavi Hesabi, Z ; Aboutalebi, S. H ; Sadrnezhaad, S. K ; Sharif University of Technology
2012
Abstract
The effect of high-energy ball milling on the textural evolution of alumina nanopowders (compaction response, sinter-ability, grain growth and the degree of agglomeration) during post sintering process is studied. The applied pressure required for the breakage of the agglomerates (P y) during milling was estimated and the key elements of compressibility (i.e. critical pressure (P cr) and compressibility (b)) were calculated. Based on the results, the fracture point of the agglomerates decreased from 150 to 75 MPa with prolonged milling time from 3 to 60 min. Furthermore, the powders were formed by different shaping methods such as cold isostatic press (CIP) and uniaxial press (UP) to better...
Effect of nanoscaled reinforcement particles on the structural evolution of aluminium powder during mechanical milling
, Article Powder Metallurgy ; Volume 52, Issue 2 , 2009 , Pages 151-157 ; 00325899 (ISSN) ; Kamrani, S ; Simchi, A ; seyed Reihani, M ; Sharif University of Technology
2009
Abstract
This paper presents experimental results on the synthesis of nanostructured aluminium matrix nanocomposite powders by comilling of nanoscaled SiC and Al2O3 particles and micrometric aluminium powder. The effect of the nanometric reinforcement particles on the mechanical milling (MA) process of the soft matrix was studied by scanning electron microscopy, X-ray diffraction (XRD), transmission electron microscopy, laser particle size analyser and standard metallographic techniques. It was found that at the early stage of milling, the nanoparticles are smeared on the surface of the aluminium powder and thus do not significantly contribute in the MA process. As the milling continues, the hard...
Synthesis and characterization of Al-SiC nanocomposites produced by mechanical milling and sintering
, Article Advanced Composite Materials ; Volume 20, Issue 1 , 2011 , Pages 13-27 ; 09243046 (ISSN) ; Razavi Hesabi, Z ; Riedel, R ; Seyed Reihani, S. M ; Sharif University of Technology
2011
Abstract
Aluminum powder and various volume fractions of SiC particles with an average diameter of 50 nm were milled by a high-energy planetary ball mill to produce nanocrystalline Al-SiC nanocomposite powders. Double pressing/sintering process was used to consolidate powders to cylindrical specimens. It was shown that a double cycle of cold pressing and sintering can be utilized to obtain high density Al-SiC nanocomposite parts without using a hot-working step. High resolution scanning electron microscopy (HRSEM), X-ray diffraction (XRD) and laser particle size analyzer (PSA) were used to study the morphological and microstructural evolution of nanocomposite powders and bulk samples. The role of...
Fabrication and characterisation of ultrafine-grained Al-5vol%Al 2O3 nanocomposite
, Article International Journal of Nanomanufacturing ; Volume 5, Issue 3-4 , 2010 , Pages 341-351 ; 17469392 (ISSN) ; Simchi, A ; Seyed Reihani, S. M ; Simancik, F ; Sharif University of Technology
2010
Abstract
Nanocrystalline Al-5vol%Al2O3 nanocomposite was synthesised by mechanical milling of a mixture containing nanometric alumina with an average particle size of 35 nm. Morphology of as-synthesised powder was investigated by SEM while crystallite size of Al matrix was determined by XRD analysis. The results confirmed formation of nanocrystalline Al matrix induced by severe plastic deformation during mechanical milling. Nanocomposite bars were produced by hot powder extrusion route. TEM investigation of as-extruded nanocomposite revealed formation of elongated grains along the extrusion direction decorated by alumina nanoparticles. Tensile and compressive properties of as-extruded nanocomposite...
Incorporating aspect ratio in a new modeling approach for strengthening of MMCs and its extension from micro to nano scale
, Article Advanced Composite Materials ; Volume 19, Issue 4 , Apr , 2010 , Pages 299-316 ; 09243046 (ISSN) ; Bagheri, R ; Zebarjad, S. M ; Razavi Hesabi, Z ; Sharif University of Technology
2010
Abstract
The strengthening behavior of particle reinforced metal-matrix composites is primarily attributed to the dislocation strengthening effect and the load transfer effect. To account for these two effects in a unified way, a new multi-scale approach is developed in this paper incorporating the aspect ratio effect into the geometrically necessary dislocation strengthening relationships. By making use of this multi-scale approach, the deformation behavior of metal-matrix composites (MMCs) and metal-matrix nanocomposites (MMNCs) as a function of size, volume fraction, aspect ratio, etc. of the particles has been investigated. Comparison with the previously proposed models and the available...
Hierarchical Optical Network-on-Chip Based on Hypercube Topology
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though...
Architecture of Reconfigurable Optical Network-on-Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with...
Modified WK-Recursive Topology for an Optical Network-on-Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of...
Reliablity-Aware Energy Management for Mixed-Criticality Systems on Multicores
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
Integrating functionalities of different-criticality levels on a shared computing platform known as Mixed-Criticality Systems (MCSs) has been noticed recently in research and industrial designs. Due to the battery-operated nature of some MCSs and different reliability requirement for tasks, joint energy and reliability management is crucial in these systems. Another important issue in these systems which is rarely addressed in previous works is tolerating permanent faults. In this thesis, we propose two comprehensive schemes: MC-4S and MC-2S which guarantee to tolerate permanent faults and maintaining the system reliability with respect to the transient faults. In addition, guaranteeing the...
Aging Mitigation for Arithmetic and Logic Unit of a Processor
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
Shrinking the dimensions of transistors in recent fabrication technologies has led to an increase in the aging rate of chips, as the most important challenge in reliability of new processors. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effect of transistor shrinkage. These two effects decrease the switching speed of transistors by increasing its threshold voltage over time. Threshold voltage shift causes timing violation in combinational parts of circuit and decreases the robustness of sequential parts against soft errors. Between different units of a processor, Arithmetic and Logic Unit (ALU) is one of the most susceptible units...
An Efficient Hardware Trojan Detector Using On-chip Ring Oscillator
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
Nowadays integrated circuits are extremely vulnerable to hardware trojans (HT). Hardware trojans can be injected into the ICs in design or fabricate phase, and damage system’s functionality or security. In this thesis, we first describe hardware trojan definition, classification and types of HTs, negative effects, detection ways and analysis of them. Then we propose a new solution in order to solve the negative points of previous methods
A Scan Chain-Based Aging Monitoring Scheme for Detection of Recycled Chips
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different...
A Scheme for Counterfeit Chip Detection Using Scan Chain
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects relability of the chips is modifications or additions with malicious intension, known as Harware Trojans, which are easily applicable during design and manufacturing phase of chip. This study intends to introduce a model based on the scan chain, a method is provided for intellectual property protection. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require...
Accelerating Perfect and Imperfect Loops Using Reconfigurable Architectures
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
With the widespread use of mobile applications, multimedia and telecommunications, speed of execution has become important. The computation-intensive portions of applications, i.e., loops, devote a significant percentage of their implementation time. Thus, in this thesis, a new method is introduced which greatly increases the execution speed of the loops. Loops are often implemented on coarse-grained reconfiguration architecture (CGRAs) for acceleration, which is a promising architecture with high performance and high power efficiency in comparison to FPGA. In this regard, to reduce the execution time of two-level nested loops, if there are several innermost loops, first, we fuse them, then...
Improving Manufacturing Yield and Life Cycle of Special Purpose SIMT Processors for Inexact Computing
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
The downscaling of feature size and higher process variation in COMS nano-technology are anticipated to introduce higher manufacturing anomalies. On the other hand, designs are getting more complicated due to more innovative applications where they need higher numbers of transistors. Because of these issues, integrated circuits manufacturing has become more complicated than before. Complexity in manufacturing process increases the probability of the defects in chips. This phenomenon reduces the fabrication yield. Conventional methods like fault tolerant techniques, defect tolerant techniques and redundancy are not separately good enough for improving manufacturing yield. On the other hand,...
Improving Performance of GPGPU Considering Reliability Requirements
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
In recent years, GPUs are becoming ideal candidates for processing a variety of high performance applications. By relying on thousands of concurrent threads in applications and the computational power of large numbers of computing units, GPGPUs have provided high efficiency and throughput. To achieve the potential computational power of GPGPUs in broader types of applications, we need to apply some modifications. By understanding the features and properties of applications, we can execute them in a more proper way on GPUs. Therefore, considering applications’ behavior, we define 5 different categories for them. Every category has special definitions, and we change the configuration of GPU...
Hardware Trojan Detection: A Size-Aware Approach
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
With constant increase in the rate of VLSI circuits manufactured in sites separate from the designers and computer architects, global concern regarding the possibility of integration of malware by the manufacturing foundries has arisen. Particularly, one main issue that affects reliability of the chips is modifications or additions with malicious intention,known as Hardware Trojans, which are easily applicable during design and manufacturing phase of chips. There has been an increasing fraud in chip-set manufacturing. Hardware Trojans may leak confidential information outside the chip, to the attacker, may alter the function of circuit, or completely fail a system. Hence search for new...
High Speed CDMA Communication in Optical Network on Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
As the number of processing cores on a single chip continues to grow, the need for a high band width, low power communication structure, will be the most important requirements of next generation chip multiprocessors. Today, a major part of power consumption in multi core architectures belongs to interconnects. Due to these facts, reducing consuming power, as well as supporting high performance, is concerned in these architectures. The concept of “network-on-chip” emerged to improve the performance of CMPs. But now a day, considering the circumstances of power budges, it’s incapable of presenting new strategies to decrease consuming power and delay. However, optical interconnects have the...
A modified patch propagation-based image inpainting using patch sparsity
, Article AISP 2012 - 16th CSI International Symposium on Artificial Intelligence and Signal Processing ; 2012 , Pages 43-48 ; 9781467314794 (ISBN) ; Mahdavi-Amiri, N ; Sharif University of Technology
2012
Abstract
We present a modified examplar-based inpainting method in the framework of patch sparsity. In the examplar-based algorithms, the unknown blocks of target region are inpainted by the most similar blocks extracted from the source region, with the available information. Defining a priority term to decide the filling order of missing pixels ensures the connectivity of object boundaries. In the exemplar-based patch sparsity approaches, a sparse representation of missing pixels was considered to define a new priority term. Here, we modify this representation of the priority term and take measures to compute the similarities between fill-front and candidate patches. Comparative reconstructed test...