Sharif Digital Repository

Fast locking PLL-based wide-band frequency synthesizers used in high performance RF transceivers often require multi-band voltage controlled oscillator (VCO). These types of frequency synthesizers employ both discrete and continuous tuning mechanisms to satisfy wide frequency range and low VCO tuning gain simultaneously. To facilitate discrete tuning mechanisms, an auxiliary digital loop is required in order to select proper band of VCO. This digital loop is called adaptive frequency calibration (AFC). In this paper two methods of previous AFC architectures are discussed and improved to gain the minimum possible lock time of PLL. Then, these two methods are simulated and implemented over... 

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, XOR extraction, and carry-signalmapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted XORs into half/full-adders to make a very fast debugging algorithm. This approach is robust... 

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, xor extraction, and carry-signal mapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted xors into half/full-adders to make a very fast debugging algorithm. This approach is... 

Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency... 

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB... 

This paper presents a methodology for the design of Ka/Q-band monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs). Design techniques are introduced to reduce chip area and to improve bandwidth (BW). These techniques are applied to the design of a 31-39-GHz 5-W HPA implemented on a 0.1-μm AlGaAs-InGaAs pseudomorphic HEMT (pHEMT) technology. With chip dimensions of 3.35 × 3.2 mm2, the HPA achieves 24% average power-added efficiency (PAE) over the frequency band, while maintaining an average 22-dB small-signal gain. A balanced high-power amplifier (BPA) is also presented, which combines the power of two 5-W HPA cells to deliver peak 8.5-W output power (Pout) in the... 

We generalize the double negation construction of Boolean algebras in Heyting algebras to a double negation construction of the same in Visser algebras (also known as basic algebras). This result allows us to generalize Glivenkos theorem from intuitionistic propositional logic and Heyting algebras to Vissers basic propositional logic and Visser algebras  

This paper presents two integrated concurrent dual-band class-J power amplifiers (PAs) in AlGaAs-InGaAs pHEMT technology. Design flexibility of class-J space is employed to explore the availability of a dual-band PA where the center frequency of the second band is twice the center frequency of the first band (f2=2f1). The theoretical formulations are developed for f2=2f1 case, for which it is not feasible to obtain high efficiencies using class-F-1, class-F, and other high-efficiency modes. A proof of concept 5/10-GHz class-J PA is manufactured in a 0.1- μm GaAs pHEMT technology. The proposed PA delivers 26.9- and 26-dBm output power with peak power added efficiencies (PAEs) of 49% and 46%... 

In this paper, the class-J mode of operation is investigated when sinusoidal, half-sinusoidal (HS), triangle, pulse, and reduced conduction angle voltage waveforms are shaped at the gate node of the transistor. Output power, maximum power-added efficiency (PAE), large signal gain (LSG), and load-pull contours are presented and compared for each input signal. It is shown that PAE of a class-J power amplifier (PA) is improved when an HS voltage is realized at the gate node of the transistor. This enhancement can also be observed for a pulse input with 20% duty cycle, however, at the expense of reduced output power and LSG. A proof-of-concept, two-stage class-J PA is designed and fabricated in... 

This paper presents the theoretical introduction and experimental validation of the "Class-J2 Mode Power Amplifier," which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J2 PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to... 

Recently, class-J₂ operation mode has been proposed in the literature for high-efficiency power amplifier (PA) design. It has been shown that the output power (Pout) of a class-J₂ PA can be 1.5 dB higher than Pout of a class-J counterpart, whereas the theoretical drain efficiency of the class-J₂ mode can be as high as 83%. This paper is devoted to introduce and characterize the class-J₂₃ mode of operation, which is the generalized form of the class-J₂ mode and provides a new design space to realize highly efficient PSs. In this new PA mode, the third-harmonic voltage is also included in the drain voltage of the transistor to increase the drain efficiency up to 95.4% in theory. Design space... 

A practical coplanar Josephson junction left-handed transmission line based on a step-edge junction technique is proposed in high-temperature superconductor technology and analyzed by electromagnetic simulations. The layout is designed for monolayer Yttrium Barium Copper Oxide thin film fabrication process. The propagation stopbands are tunable by controlling bias currents of Josephson junction arrays acting as parallel inductors for unit cells of the transmission line. Unlike the reported designs, each unit cell of our left-handed transmission line is independently biasable due to dc isolation of the unit cells along the transmission line. Being individually biasable is practically... 

Josephson junction in superconductor circuits and metamaterials is modeled as a tunable inductance. The Josephson inductance is tunable by the bias current passing through it and can be tuned from an initial value to a very large value as much as one can push bias current near the critical current but not exceeding it. Tunability by bias current allows design of programmable metamaterials with flexible functions in microwave regime. In High-Temperature Superconductivity (HTS) tunable metamaterials, Josephson junctions should be used in series configuration to give usable tunable inductance. Each Step-Edge Josephson junction (SEJs) in HTS has a critical current that is dependent on its... 

Recently, class-J₂ operation mode has been proposed in the literature for high-efficiency power amplifier (PA) design. It has been shown that the output power (Pout) of a class-J₂ PA can be 1.5 dB higher than Pout of a class-J counterpart, whereas the theoretical drain efficiency of the class-J₂ mode can be as high as 83%. This paper is devoted to introduce and characterize the class-J₂₃ mode of operation, which is the generalized form of the class-J₂ mode and provides a new design space to realize highly efficient PSs. In this new PA mode, the third-harmonic voltage is also included in the drain voltage of the transistor to increase the drain efficiency up to 95.4% in theory. Design space... 

Josephson junction in superconductor circuits and metamaterials is modeled as a tunable inductance. The Josephson inductance is tunable by the bias current passing through it and can be tuned from an initial value to a very large value as much as one can push bias current near the critical current but not exceeding it. Tunability by bias current allows design of programmable metamaterials with flexible functions in microwave regime. In High-Temperature Superconductivity (HTS) tunable metamaterials, Josephson junctions should be used in series configuration to give usable tunable inductance. Each Step-Edge Josephson junction (SEJs) in HTS has a critical current that is dependent on its... 

Josephson junction in superconductor circuits and metamaterials is modeled as a tunable inductance. The Josephson inductance is tunable by the bias current passing through it and can be tuned from an initial value to a very large value as much as one can push bias current near the critical current but not exceeding it. Tunability by bias current allows design of programmable metamaterials with flexible functions in microwave regime. In High-Temperature Superconductivity (HTS) tunable metamaterials, Josephson junctions should be used in series configuration to give usable tunable inductance. Each Step-Edge Josephson junction (SEJs) in HTS has a critical current that is dependent on its... 

In this paper a complete design of a high speed optical human motion tracking system has been described for biomechanical human motion analysis and animation craft applications. The main core of the image processing unit that is implemented by the differential algorithm procedure and some intelligent and conservative procedures that facilitate the search algorithm have also been proposed and implemented for the processing of human motions tracking images. In the next step an optimized modified direct linear transformation (MDLT) method has been used to reconstruct 3D locations of markers as an input data for animation unit. The low computational cost and the high precision in detecting and... 

This study presents a hybrid harmony search algorithm (HHSA) to solve engineering optimization problems with continuous design variables. Although the harmony search algorithm (HSA) has proven its ability of finding near global regions within a reasonable time, it is comparatively inefficient in performing local search. In this study sequential quadratic programming (SQP) is employed to speed up local search and improve precision of the HSA solutions. Moreover, an empirical study is performed in order to determine the impact of various parameters of the HSA on convergence behavior. Various benchmark engineering optimization problems are used to illustrate the effectiveness and robustness of... 

Autism Spectrum Disorders (ADS), with unknown etiology, is one of the most understudy fields of research worldwide that requires complicated and delicate analytical study methods. The purpose of this study was to compare active regions of Brain Default Mode Network (DMN) using Group Independent Component Analysis (6ICA) among resting state patients with Autism Disorder and healthy subjects. Default Mode Network consists of posterior cingulate cortex (PCC), lateral parietal cortex/angular gyrus retrosplenial cortex, medial prefrontal cortex, superior frontal gyrus, parahippocampal gyrus and temporal lobe shows more prominent activity in passive resting conditions. The diagnosis of autism... 

Autism Spectrum Disorders (ADS), with unknown etiology, is one of the most understudy fields of research worldwide that requires complicated and delicate analytical study methods. The purpose of this study was to compare active regions of Brain Default Mode Network (DMN) using Group Independent Component Analysis (6ICA) among resting state patients with Autism Disorder and healthy subjects. Default Mode Network consists of posterior cingulate cortex (PCC), lateral parietal cortex/angular gyrus retrosplenial cortex, medial prefrontal cortex, superior frontal gyrus, parahippocampal gyrus and temporal lobe shows more prominent activity in passive resting conditions. The diagnosis of autism...