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LAXY: a location-based aging-resilient Xy-Yx routing algorithm for network on chip

Rohbani, N ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/TCAD.2017.2648817
  3. Abstract:
  4. Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is based on the fact that dimension-ordered routing algorithms imposes the highest traffic load on the central nodes in mesh topologies. To balance the traffic over the network, certain routers at the east and the west of NoC, with dimension-order XY routing, statically are configured as YX. Various configurations have been explored for LAXY and the simulations show a specific configuration, called Fishtail, increases mean time to failure of the routers and interconnects by about 42% and 56%, respectively. Moreover, by balancing the load over the network, LAXY improves overall packet latency by about 7% in average, with negligible area overhead. © 1982-2012 IEEE
  5. Keywords:
  6. Hot carrier injection (HCI) ; Negative bias temperature instability (NBTI) ; Network on chip (NoC) ; Routing algorithm ; Traffic balancing ; Electric currents ; Electromigration ; Field effect transistors ; Hot carriers ; Integrated circuit interconnects ; Nanotechnology ; Negative bias temperature instability ; Negative temperature coefficient ; Network routing ; Routers ; Routing algorithms ; Servers ; Thermodynamic stability ; Dimension-ordered routing ; Hot carrier injection ; Interconnection architecture ; Mean time to failure ; Nanoscale technologies ; Network experiences ; Network-on-chip(NoC) ; Network-on-chip
  7. Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 36, Issue 10 , 2017 , Pages 1725-1738 ; 02780070 (ISSN)
  8. URL: https://ieeexplore.ieee.org/document/7807235