Reducing Power of On-chip Networks by Exploiting Latency Asymmetry of Router’s Pipeline Stages, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
NOCs contribute to a large portion of a many-core SOC power consumption. A significant fraction of the mentioned power consumption is due to the buffers, crossbar and the links. Thus, in this thesis, a new method would be introduced which reduces the power consumption of the NOCs in large scale. This method utilizes the latency asymmetry of router pipeline stages for dynamic power reduction and uses different voltage swings for buffers, links and the crossbar in order to decrease the dynamic power consumption while maintaining the performance. Moreover, since the static power consumption has gained a noticeable importance in recent years, a method for degrading this power component is also...
Cataloging briefReducing Power of On-chip Networks by Exploiting Latency Asymmetry of Router’s Pipeline Stages, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
NOCs contribute to a large portion of a many-core SOC power consumption. A significant fraction of the mentioned power consumption is due to the buffers, crossbar and the links. Thus, in this thesis, a new method would be introduced which reduces the power consumption of the NOCs in large scale. This method utilizes the latency asymmetry of router pipeline stages for dynamic power reduction and uses different voltage swings for buffers, links and the crossbar in order to decrease the dynamic power consumption while maintaining the performance. Moreover, since the static power consumption has gained a noticeable importance in recent years, a method for degrading this power component is also...
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