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Evaluation of Fault Tolerance for SRAM-Based FPGAs by Fault Injection into Configuration Bits

Abolhassani Ghazaani, Elyas | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44804 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of a fault injection framework. This thesis combines the advantages of previous fault injection frameworks by presenting a full-featured framework that supports a set of properties simultaneously.First, it is flexible. The user can define desired parameters to manage fault injection scenarios. Second, it provides portability, meaning that it can be used for a wide variety of FPGA devices. This property is provided through partial reconfiguration via JTAG interface. Third, it works in a non-intrusive manner, which guarantees accurate reliability measures. A novel methology has been proposed to ensure non-intrusiveness of framework into the design under test. Finally, the process of injecting fault, running circuit under test and repairing fault is taken in 17 milliseconds on average. The framework is structured as hardware-software units to gain mentioned properties. The proposed framework is the first of its type working on Xilinx Virtex-6 FPGA device; however, using mentioned device required reversed engineering procedures in order to learn its configuration frame addressing structure. Furthermore, well-known fault tolerant techniques for SRAM-based FPGAs have been evaluated in this project. Using proposed fault injection framework, the reliability of coarse-grain TMR, fine-grain TMR, RoRA and, Duplication with Comparison have been assessedby fault injection into configuration memory of the device. Conducted fault injection experiments show that 2% of injected faults in TMR-based techniques result in wrong answers, with this percentage being 3% for DWC. These effective faults were located on the configuration resources occupied by voters of TMR or comparators of DWC. Moreover, it has been observed that the intensified volume of redundancy in CGTMR has not led to increased reliability. This is because the output voters were still vulnerable to SEU
  9. Keywords:
  10. Reliability Evaluation ; Reconfigurable Systems ; Fault Injection ; Field Programmable Gate Array (FPGA) ; Static Random Access Memory (SRAM)Cell

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