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Energy Efficient Concurrent Test of Switches and Links for Networks-On-Chip

Alamian, Sanaz | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43802 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shahin
  7. Abstract:
  8. Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand. According to the importance of data transferring speed in today’s chips, the concurrent test that has slightest influence on the process of data transferring between processing cores is considered.
    First of all in this thesis, we will become familiar with the concept of network-on-chip and its characteristics. Then we will evaluate the fault models and testing methods in these networks. On the next step, the suggested idea will be presented. Based on this idea, each router will test its own structure and the previous link, by routing data packets which the router is supposed to route. In order to avoid deadlocks and dropping data packets, and make a fault tolerant system, the process of routing will be controlled.
    At the end, in order to evaluate the suggested idea, this idea has been simulated and network’s throughput, fault coverage, latency, area overhead and power consumption of it, has been compared with the original network (without any ideas to test), then with the similar previous project and the advantages of this idea will be disclosed
  9. Keywords:
  10. Network-on-Chip (NOC) ; Power Consumption ; Links ; Router ; Network Switch ; Fault-Detection Coverage ; Concurrent Test

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