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Evaluating and Improving the Reliability of Reversible Adiabatic Logic Styles

Akbar, Reza | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43571 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. Adiabatic logic families are a group of logic circuits which operate based on adiabatic principles to tremendously reduce power consumption. These families have basic difference with common logic families in transistor level structure and there signals are not quadrangular but trapezoidal. Also, in these systems the source lines and clock pulse are the same. Research on Adiabatic families needs theoretical information in reversible computing. So we will start this project with explaining fundamental information in this field. After that some of these logic families are introduced and three important and widely used of them (SCRL-RERL-2LAL) are chosen to simulate. In each of these families the buffer circuits and four-floor shift register are designed and simulated with Hspice. Then, we compare the designed circuits in mentioned logics with each other and the conventional C-CMOS logic family from the aspect of area, delay, power and reliability. As a result, the power consumption is considerably decreased compared to the conventional logic so that, even the 2LAL family which has the worst rank for consuming power, reduces the consumption nearly 60000 times. RERL consumes the least power and 2LAL has the worst situation among these families. Among the other parameters, reliability is the most important one and the attenuation caused by adiabatic circuits in reliability can be resolved with using hardware redundancy without power concerns. From the area aspect, which has not been a concern to designers these early years, 2LAL is the best logic while RERL is the worst one. From the delay aspect 2LAL is the best logic and SCRL is the worst one. Also, RERL preserves the best reliability among these families and its circuits unlike the other adiabatic logics which reinforce faults, annihilates the faults. 2LAL family has the lowest reliability and almost 30 present of shown fault caused by small error that are amplified. Note that in this project fault injection model is considered SEU
  9. Keywords:
  10. Reliability ; Power Consumption ; Adiabatic Circuits ; Reversible Computing

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