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High-level optimization of integer multipliers over a finite bit-width with verification capabilities

Sarbishei, O ; Sharif University of Technology | 2009

630 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/MEMCOD.2009.5185378
  3. Publisher: 2009
  4. Abstract:
  5. Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches. © 2009 IEEE
  6. Keywords:
  7. Binary representations ; Bit-Width ; Care optimization ; Conventional optimization ; Efficient architecture ; Logic optimization ; Multiply-accumulator units ; Optimization approach ; Residue number system ; Formal methods ; Optimization ; Signal processing ; Integer programming
  8. Source: 2009 7th IEEE-ACM International Conference on Formal Methods and Models for Co-Design, MEMOCODE '09, Cambridge, MA, 13 July 2009 through 15 July 2009 ; 2009 , Pages 56-65 ; 9781424448067 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/5185378