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Performance and Power-Efficient Design of Non-Volatile Shared Caches in Multi-Core Systems

Shafahi, Mohammad Hassan | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43646 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. Emerging memory technologies such as STT-RAM, PCM and resistive RAM are probable technologies for caches and main memories of the future multi-core architectures. This is because of their high density, low leakage current and non-volatility. Nevertheless, the overhead of latency and energy consumption of write operation in these technologies are the main open problems. Previous works have suggested various solutions, in architecture and circuit levels, to reduce the writing overheads. In this research, we study the integration of STT-RAM in 3-dimensional multi-core environments; and propose solutions to address the problem of writing overheads when using this technology in cache architectures in an NoC. In order to improve the performance and throughput of the system, in this project we offer a hierarchical scalable scheduling algorithm which is based on the observations of the requests to access the memory banks, and also the difference between the times required to write to, and read from these memories. Simulation results show that the proposed method can improve the average access latency in multithreaded and multiprogrammed programs by 28.3% and 41% respectively compared to the baseline system. Also by considering full input buffers and changing the transmission time, the average access latency is improved by 37.3% and 52.4% for multithreaded and multiprogrammed programs respectively
  9. Keywords:
  10. Network-on-Chip (NOC) ; Non-Volatile Memory ; Nonuniform Cache Memory

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