Hardware Redundancy in Fault-Tolerant Digital Systems: A VHDL Approach to Evaluate TMR Robustness, M.Sc. Thesis Sharif University of Technology ; Jahed, Mehran (Supervisor)
Abstract
Triple Module redundancy (TMR) is a commonly used approach to increase reliability in space applications. Applying this method, triple modules and voting circuits are implemented in a field programmable gate array (FPGA). In TMR systems when a single event upset (SEU) occurs, the voting circuit neglects the failure value of a module receiving the SEU and takes a correct value from the other two modules. The present TMR approach utilized for the combinational and sequential logic on the gate level shows that it is possible to write hardware description language (VHDL) code in a structured yet high level coding style to obtain the required redundancy. However using VHDL, the level of required...
Cataloging briefHardware Redundancy in Fault-Tolerant Digital Systems: A VHDL Approach to Evaluate TMR Robustness, M.Sc. Thesis Sharif University of Technology ; Jahed, Mehran (Supervisor)
Abstract
Triple Module redundancy (TMR) is a commonly used approach to increase reliability in space applications. Applying this method, triple modules and voting circuits are implemented in a field programmable gate array (FPGA). In TMR systems when a single event upset (SEU) occurs, the voting circuit neglects the failure value of a module receiving the SEU and takes a correct value from the other two modules. The present TMR approach utilized for the combinational and sequential logic on the gate level shows that it is possible to write hardware description language (VHDL) code in a structured yet high level coding style to obtain the required redundancy. However using VHDL, the level of required...
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