Sharif Digital Repository

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This approach is based on the differential configuration for the quantizer while maintains its inherent dynamic element matching property. Consuming no additional power and area compared to the conventional scheme, this architecture can eliminate the even orders of harmonic distortion and achieve higher linearity. Theoretical analysis for signal to quantization noise, power and area consumption and mismatch effect is provided. To illustrate the effectiveness of the new architecture in continuous time modulators, a modulator with 640 MHz sampling rate utilizing the mentioned quantizer is simulated in... 

A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the bias circuit is presented. A 1.8v 2.4GHz differential LC VCO is designed in a 0.18u CMOS technology using this technique. With the proposed switching technique, the close in phase noise is improved as much as 15dB at 500 kHz offset. The simulated phase noise at the offsets of 500 kHz and 1 MHz is... 

In this paper a self-oscillating mixer is presented fundamental signal generated by the oscillator subcircuit in the mixing process. The oscillator core consumes 3mA of current from a 1.8 V DC supply and results in an output power of -0.867 dBm per oscillator, and a measured phase noise of -91, -102 and -108 dBc/Hz at 100 KHz, 600 KHz and 1 MHz from the carrier, respectively. In the mixing process the proposed mixer achieved IIP3 of 0 dBm with conversation gain of 1.93 dB. The circuit was designed and simulated in 0.18-μm CMOS technology by ADS2010  

This paper presents a low voltage low noise open loop automatic amplitude control method for voltage-controlled oscillators (VCO's). In this method a feedback mechanism keeps the VCO at its optimum amplitude over temperature and process variations and then the loop is broken to avoid noise injection form the control circuitry to the VCO. The loop does not add extra noise to the VCO. Based on the proposed method, a low voltage low noise LC-VCO was designed for a low phase noise application in TSMC 0.18 micron RFCMOS technology. Simulations show considerable improvement in the phase noise with the application of the proposed method  

This paper presents the design and implementation of a low power, low voltage, continuous time delta sigma modulator for audio band in 90 nm CMOS technology. A VCO-based integrator and quantizer are used. Inherent dynamic element matching (DEM) of the quantizer eliminates the need for explicit DEM logic which results in a short excess-delay and power saving. Simulation results show that the modulator achieves 78 dB SNDR and 87 dB SNR in a 20 kHz input bandwidth and dissipates 106 μW from 1 V supply. The power consumption for different parts is discussed  

A new phase noise calculation method is proposed in which noise sources are modeled with single tone sources. It uses a nonlinear frequency-domain analysis to calculate total gain from noise sources to the output phase noise. This single tone (ST) simulation directly calculates noise frequency contributions and is much faster than Hajimiri's impulse sensitivity function (ISF) method. A quadrature VCO has been implemented in TSMC 0.18-μm CMOS and the predicted phase noise matches measurement. © 2009 IEEE  

Control and stabilisation of the resonant converters are essential problems in power electronics. The conventional model of the dc-dc series resonant converter (SRC) is derived using the sinusoidal approximation and generalised averaging followed by linearisation about an operating point. This model involves considerable approximation and is not applicable for large variation of load and supply voltage. The authors have already proposed a direct piece-wise affine (DPWA) modelling and control approach for the SRC that operates above resonant frequency. However, the DPWA technique is not applicable to an SRC that operates below resonance because of the presence of harmonics. In this study, a... 

A systematic method to design high power and high efficiency mm-wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77-GHz two-stage (differential) VCO is designed in a 65-nm CMOS... 

Fast locking PLL-based wide-band frequency synthesizers used in high performance RF transceivers often require multi-band voltage controlled oscillator (VCO). These types of frequency synthesizers employ both discrete and continuous tuning mechanisms to satisfy wide frequency range and low VCO tuning gain simultaneously. To facilitate discrete tuning mechanisms, an auxiliary digital loop is required in order to select proper band of VCO. This digital loop is called adaptive frequency calibration (AFC). In this paper two methods of previous AFC architectures are discussed and improved to gain the minimum possible lock time of PLL. Then, these two methods are simulated and implemented over... 

DC-DC quasi-resonant converters (QRC) have the advantage of reducing switching losses and electromagnetic interference (EMI) which are the main disadvantages of high frequency power converters. The control and stabilization of these converters have always been a challenge. Traditionally, the dynamical model of the QRC is obtained using state space averaging followed by linearization about an operating point. The major flaw of this method is that state variables have large variations; thus, the linearized averaged model is not valid. Therefore, it is necessary to obtain a more precise model for the aim of stability analysis and controller design. Due to semiconductors switching, QRCs are... 

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 n ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400-3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to... 

This article presents the theory and implementation of a quadrature and differential RF front-end receiver. Combining balun, low-noise amplifier (LNA), mixer, and oscillator in a single stage, the proposed circuit, named the Blixator, is well suited for low-power applications. The baseband's transimpedance amplifier (TIA) also shares part of its dc current with the Blixator cell, resulting in sub-milliwatt power consumption. To avoid additional power and area by quadrature LO generation, the I/Q signals are generated at RF, employing the inductors already required for providing the dc current path of the LNA transistors. The expressions for gain, noise figure (NF), and phase noise of the... 

This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped VCO oscillating signal which effectively maximizes oscillating signal slope at zero crossing points resulting in-phase-noise degradation. In addition, by shortening down converted noise power around oscillating signal second harmonic, more phase-noise suppression has been achieved. A comprehensive analysis for frequency and amplitude deviations as high as 20% for third harmonic and its effect on output phase-noise suppression has been discussed. In the followings, a comprehensive analysis...