Sharif Digital Repository

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply  

A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE  

In double tail comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, to save power and improve offset. In fact, when the latch is activated the pre-amplifier output differential voltage is still growing but the latch finishes the comparison before the maximum differential gain is formed and applied to the latch. In this paper, a comparator is proposed in which the preamplifier is turned off when the maximum gain is... 

Quantum-dot Cellular Automata (QCA) is a very interesting nano-scale technology. Extremely small feature size and ultra-low power consumption are the most important features of QCA compared to CMOS. Counters are considered as one of the most fundamental components in sequential circuits. Previous QCA synchronous counters (QSCs) have been designed and simulated using two methods. In the first method, QSCs utilize direct mapping flip-flop designs in CMOS technology to QCA. In the second method, QSCs are designed with the inherent capability of QCA technology. Despite being attractive, mentioned approaches have constraints (i.e. long wire length and area issues). In this brief, design and... 

This article reports the development of a new smart electrocardiogram (ECG) monitoring system, consisting of the related hardware, firmware, and Internet of Things (IoT)-based web service for artificial intelligence (AI)-assisted arrhythmia detection and a complementary Android application for data streaming. The hardware aspect of this article proposes an ultralow power patch sampling ECG data at 256 samples/s with 16-bit resolution. The battery life of the device is two weeks per charging, which alongside the flexible and slim (193.7 mm times62.4 mm times8.6 mm) and lightweight (43 g) allows the user to continue real-life activities while the real-time monitoring is being done without...