Sharif Digital Repository

A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE  

Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012... 

Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...