Sharif Digital Repository

By puncturing the Reed-Solomon codes with the block lengths of 2 m, it is possible to design systematic and nonsystematic codes with arbitrary block lengths and rates that can be decoded using FFT. Because the Reed-Solomon (RS) codes are maximum distance separable (MDS), the resultant codes keep this property as well. The codes are constructed over prime fields as opposed to the conventional practice of extension fields, and hence additions and multiplications are simple mod operations and there is no need to use polynomials and look-up tables. © IEE, 2005  

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity... 

The islanding of a distributed generation (DG)-fed distribution system generally results in frequency drop, which means less power is generated than it is needed. The only way of dealing with this problem is shedding loads as the system cannot generate any more electricity. Load shedding is intended to restore balance between generated and consumed power. This paper proposes a new method for load shedding based on the rate of change of frequency (RoCoF) at the first step and on voltage drop at subsequent steps. For this purpose, three lookup tables were created in order to prioritize loads to be shed according to the willingness of subscribers to pay and the RoCoF. The strength of the... 

A comprehensive approach is proposed to manage landing sequences and their associated trajectories for an arbitrary number of aircraft in the vicinity of a controlled aerodrome. The current approach, similar to that of "first come, first served," could consider different types of priorities as well as emergencies. The approach is especially useful to combine unstructured free-flight trajectories with structured ones during the approach phase of the flight A comprehensive cost function considers the relative size of all aircraft together with their relative speeds and flight directions. This helps optimize the amount of fuel consumption while respecting separation minima. Resulting... 

Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration... 

A novel architecture for QR decomposition-based recursive least squares is presented. It offers low latency for applications where the channel equalization and adaptive filtering are mandatory. This approach reduces the computations by rewriting the equations in a manner that lets intense hardware resource sharing by reusing similar values in different computations. Moreover, precision range conversion allows for combining complex operations such as root square and division with minimum effect on the overall quantization error. Hence, an efficient lookup table-based solution has highly enhanced the performance of the design by 2.7 times with respect to the previous works  

In synchros and resolvers, brushes, and slip-rings produce a lot of noise in the output signal. Compared to encoders, the application of such position sensors in precision control systems is restricted because of their low accuracy. In this paper, a novel scheme of a brushless synchro is introduced. In this scheme, the primary and secondary windings are mounted on the stator, and the stator magnetic flux passes a certain path in the rotor with inducing voltage in the secondary winding. In this paper, a software method based on simple look-up table is used to enhance accuracy and reliability of the output signal of the proposed synchro. The operation principle of the brushless synchro is... 

The IP Lookup Process is a key bottleneck in routing due to the increase in routing table size, increasing traffic and migration to IPv6 addresses. The IP routing lookup involves computation of the Longest Prefix Matching for which existing solutions, such as BSD Radix Tries, scale poorly when traffic in the router increases or when employed for IPv6 address lookups. In this paper, we describe a CREW PRAM multiprocessor organization lookup that uses P processor for solving LPM problem. By this technique P-1 IP addresses can be looked up simultaneously thus the performance of processors increase in linear manner. First we categorize all prefixes in some groups based on their first two bytes... 

In this paper, a new and simple control method based on Direct Torque Control (DTC) of induction motors is proposed for a multi-machine system. Similar to a conventional DTC, the proposed method has two separate control loops. In the torque control loop, before selection of optimum voltage from the DTC look-up table, the system overall requirement is determined based on requirements of motors torque. Also, Switchable Master-Slave control is used in the flux control loop. The method, which is simulated for a two-parallel induction machine system, can be extended to a multi-machine system. Simulation results are also provided to investigate the performance of the proposed technique. © 2008... 

To have a complete model of a thunniform Fish-Robot, models of both body and tail are required. The dynamic model of the body is developed according to the parameters of a thunniform Fish-Robot built in MIT University, while, as the main part of this paper, the dynamic model of the tail is developed using fuzzy logic. Using experimental data and table look-up scheme, a fuzzy black box is introduced that gives the value of thrust force generated for any value of the Fish-Robot's input parameters: frequency of tail oscillation, amplitude of tail oscillation and speed of the Fish-Robot. In the second part, a trajectory fuzzy controller is designed for the Fish-Robot. The output of trajectory... 

Abstract A system designer needs to estimate the behavior of a system interconnection based on different patterns of switching which happen around an interconnect. Two different scenarios are supposed to estimate the effect of interconnect issues on system performance. First, based on a normalization technique for decreasing the number of a transfer function variables, a definitive environment for one interconnect is considered and an optimized look-up-table for the wire time delay is generated. Using some sampling methods, fast accessible look-up-tables are proposed for CAD tools in very simple and small one. A 4×4×4 table for the wire delay is introduced which results in very fast... 

To have a complete model of a thunniform Fish-Robot, models of both body and tail are required. The dynamic model of the body is developed according to the parameters of a thunniform Fish-Robot built in MIT University, while, as the main part of this paper, the dynamic model of the tail is developed using fuzzy logic. Using experimental data and table look-up scheme, a fuzzy black box is introduced that gives the value of thrust force generated for any value of the Fish-Robot's input parameters: frequency of tail oscillation, amplitude of tail oscillation and speed of the Fish-Robot. In the second part, a trajectory fuzzy controller is designed for the Fish-Robot. The output of trajectory... 

Feeding a laboratory furnace with the gaseous kerosene, the resulting two-phase turbulent flame is simulated to study the effects of injecting soot nano-particles into the inflow air on the emissions of smoke aerosol, CO, and CO2species pollutants, and the resulting radiation heat transfer. We use our past experiences in aerosol modeling of soot nano/micro particles in turbulent nonpremixed flames burning simple hydrocarbon fuels and extend them to study the effects of injecting gaseous kerosene on the aforementioned parameters. To model the evolutionary process of soot nanoparticle formation, i.e., the nucleation, coagulation, surface growth, and oxidation, we employ a two-equation soot... 

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of... 

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance... 

This paper focuses on the observer design for a 2D nano-positioner. In order to position the stage with a desired accuracy, it is required to adjust the stage displacements with a closed-loop control system. Since displacement and velocity of the main stage are not measured directly in the designed nano-positioning system, some observers should be designed to estimate these state variables using data provided by measurable variables. To this end, three different observers were designed based on neural, fuzzy and adaptive neuro fuzzy inference system (ANFIS) networks. With the purpose of obtaining data for training the observer model, a reference model is required. For this reason, the... 

Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core... 

In this work, we numerically study the effects of turbulence intensity at the fuel and oxidizer stream inlets on the soot aerosol nano-particles formation in a kerosene fuel-based combustor. In this regard, we study the turbulence intensity effects specifically on the thermal performance and nanoparticulate soot aerosol emissions. To construct our computer model, we simulate the soot formation and oxidation using the Polycyclic Aromatic Hydrocarbons PAHs-inception and the hydroxyl concept, respectively. Additionally, the soot nucleation process is described using the phenyl route, in which the soot inception is described based on the formations of tworinged and three-ringed aromatics from... 

This work numerically studies the effects of inlet air and fuel turbulators on the thermal behavior of a combustor burning the jet propulsion (JP) (kerosene-surrogate) fuel and its resulting pollutants emission including the nanoparticulate soot aerosols and aromatic compounds. To model the soot formation, the method employs a semi-empirical two-equation model, in which the transport equations for soot mass fraction and soot number density are solved considering soot nanoparticles evolutionary process. The soot nucleation is described using the phenyl route in which the soot is formed from the polycyclic aromatic hydrocarbons. Incorporating a detailed chemical mechanism described by 200...