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Accurate fault location algorithm for series compensated transmission lines
, Article IEEE Power Engineering Society Winter Meeting, 2000, 23 January 2000 through 27 January 2000 ; Volume 4 , 2000 , Pages 2527-2532 ; 0780359356 (ISBN); 9780780359352 (ISBN) ; Ranjbar, A. M ; Hadsaid, N ; Feuillet, R ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2000
Abstract
In this paper, an accurate fault location algorithm for series compensated power transmission lines is presented. A distributed time domain model is used for modeling of the transmission lines. The algorithm makes use of two subroutines for estimation of the fault distance-one for faults behind the series capacitors and another one for faults in front of the series capacitors. Then a special procedure to select the correct solution is utilized. Samples of voltages and currents at both ends of the line are taken synchronously and used to calculate the location of the fault. The proposed algorithm is independent of fault resistance and does not require any knowledge of source impedance. The...
Analysis and Control Design for TCSC and PSS in a SMIB System Using Hopf Bifurcation
, M.Sc. Thesis Sharif University of Technology ; Karimi, Masoud (Supervisor)
Abstract
Analysis and design of power systems are challenging due to ever increasing dimension of the system and also the nonlinearities involved in the system. The conventional approach is to use linear analysis tools and then investigate the nonlinear impacts by the means of computer simulations. This requires great deal of trial and error and it is not always a timely approach. In this project, we initiate a comprehensive nonlinear analysis for a single-machine infinite-bus system by studying a Hopf bifurcation in its dynamics. We use results of our nonlinear analysis to study how a capacitive compensation such as TCSC works. Subsequently, we design a nonlinear controller for a PSS to have...
Zero-power mismatch-independent digital to analog converter
, Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 11 , 2015 , Pages 1599-1605 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH
2015
Abstract
A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method
A low power 1-V 10-bit 40-MS/s pipeline ADC
, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 212-215 ; 9781457718458 (ISBN) ; Sharifkhani, M ; Gholami, M ; Sharif University of Technology
2011
Abstract
A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC...