Sharif Digital Repository

This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s... 

This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE  

A sampling and switching method for a binary weighted digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. This sampling method is proposed to reduce the switching energy. Thanks to the proposed switching method, only one reference voltage (Vcm = 1/2 Vref) is required which helps to improve the precision of the DAC along with energy reduction compared with those methods that use more than one reference voltage. The switching energy and area of the DAC reduce by 97.66% and 50% compared with the conventional binary weighted DAC  

An ultra-efficient switching method for successive approximation register ADCs is proposed. In this method, the input signals are sampled in a special fashion to reduce the switching energy. Owing to the sampling method, only one reference voltage (Vq=Vref/4) is required to implement the switching steps. Therefore, in addition to reduction in the switching energy (due to the lower supply voltage), the precision of the DAC is improved. The proposed method reduces the switching energy and area by 99.41 and 50%, respectively, compared with the conventional method. © 2016 The Institution of Engineering and Technology  

A highly energy-efficient switching method for capacitor-splitting digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. In the proposed DAC, a bottom-plate sampling method is introduced which requires only one reference voltage (Vcm = 1/2Vref) during the entire DAC switching steps. Therefore, in addition to the switching energy reduction, the precision of the DAC is increased since only one reference voltage is used. The DAC average switching energy and the area are reduced by 98.44% and 50% compared with the conventional binary weighted DAC  

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after... 

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

This paper proposes a high performance voltage tracking and current sharing among parallel connected inverters by applying optimal control and minimizing the cost function. The control system forces the voltage of load to track the voltage reference, and the current of all inverters becomes equal. Therefore, both current sharing and voltage tracking are obtained. In addition, the smallest input energy and simplicity in control circuit are the other advantages of the suggested method. To show the performance of the proposed control scheme, the simulations with two-modular practical systems are performed and the results are provided. The results indicate that the control objectives are... 

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

A dc-dc resonant converter has the advantage of overcoming switching losses and electromagnetic interference which are the main limitations of high frequency power converters. Nevertheless, the modeling and stability analysis of dc-dc resonant converters are considerably more complex than pulsewidth modulation counterparts. The conventional averaged linearized model of the resonant converter has limitations due to averaging and linearization. First of all, the linearized model has large modeling error in presence of large variations of reference voltage and input voltage. Furthermore, Converging area for stabilizing controllers is smaller in the averaged model. In order to overcome these... 

Fault detection is one of the most important tasks in fault tolerant converters. In this paper, a new method is proposed to detect the faulty cell in a cascaded H-bridge multilevel inverter. The detection technique is based on comparison of the output voltage with reference voltage made by using switching control pulses and DC-Link voltage. Because of the simplicity of this method, it is possible to use a single field-programmable gate array (FPGA) to implement this method and inverter control. The simulation and experimental results confirm the effectiveness of the proposed fault detection technique  

Linear controllers have been widely used for controlling Active Power Filters (APFs). However, due to their limitations, a tradeoff between the bandwidth of the current control loop (CCL) and the voltage control loop (VCL) need to be made to remain stable in all conditions. This tradeoff leads to imperfect usage of the APF's capacity. Nonlinear controllers can eliminate such limitations and simultaneously remain stable in all conditions. In this paper, a new nonlinear controller for controlling the output current and the DC voltage (Vdc) of an APF is proposed. Feedback linearization method is applied on the CCL and the VCL is controlled via indirect method. In this method, an auxiliary... 

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to “0” is detected as the faulty cell. Furthermore, consideration of generating the active... 

Internet of Things (IoT) devices have strict necessity for power consumption in order to achieve expected battery life. IoT nodes feature extreme power consumption range over 100 dB, between their operating modes. The main focus of this paper is to design and implement a high precision, high dynamic range, low power, and flexible power measurement system, which can be applied to different applications. The proposed system consists of a voltage regulating control loop, zero offset amplifiers, high precision analog to digital converters, and reference voltage. The proper operation of the proposed circuit are verified numerically with simulations and experimental measurements. The implemented... 

This paper proposes a novel decentralized control approach for islanded direct-current (DC) microgrids (MGs) based on model predictive control (MPC) to regulate the distributed generation unit (DGU) output voltages, i.e. the voltages of the point of common coupling (PCC). A local controller is designed for each DGU, in the presence of uncertainties, disturbances, and unmodeled dynamics. First, a discrete-time state-space model of an MG is derived. Afterward, an MPC algorithm is designed to perform the PCC voltage control. The proposed MPC scheme ensures that the PCC voltages remain within an acceptable range. Several simulation studies have been conducted to illustrate the effectiveness of... 

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a 0.18μm CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst... 

This paper describes a novel Direct Torque Control (DTC) method for adjustable speed Doubly-Fed Induction Machine (DFIM) drives which is supplied by a two-level Space Vector Modulation (SVM) voltage source inverter (DTC-SVM) in the rotor circuit. The inverter reference voltage vector is obtained by using input-output feedback linearization control and a DFIM model in the stator a-b axes reference frame with stator currents and rotor fluxes as state variables. Moreover, to make this nonlinear controller stable and robust to most varying electrical parameter uncertainties, a two layer recurrent Artificial Neural Network (ANN) is used to estimate a certain function which shows the machine...