Sharif Digital Repository

An efficient and reliable Multi-Level Cell (MLC) Spin-Transfer Torque Random Access Memory (STT-RAM) is proposed based on a Drop-And-Rearrange Approach, called DARA. Since CNN models are rather robust, less important bits are dropped, allowing important bits to be written in safe and reliable Single-Level Cell mode. Also, bits are rearranged to make the representation better aligned with memory cell characteristics. Bits with higher impact on the features value are stored in safer bit positions reducing the chance of read/write circuits to malfunction. Experimental results show that our approach provides comparable to error-free scenario reliability level, while doubling the bandwidth and... 

With the continual scaling of feature size, system failure due to soft errors is getting more frequent in CMOS technology. Soft errors have particularly severe effects in static random-access memory (SRAM)-based reconfigurable devices (SRDs) since an error in SRD configuration bits can permanently change the functionality of the system. Since interconnect resources are the dominant contributor to the overall configuration memory upsets in SRD-based designs, the system failure rate can be significantly reduced by mitigating soft errors in routing fabric. This paper first presents a comprehensive analysis of SRD switch box susceptibility to short and open faults. Based on this analysis, we... 

This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these... 

Employing a small Non-Volatile Memory (NVM) as the Persistent Journal Area (PJA) along with a DRAM-based buffer is an efficient approach to overcome DRAM vulnerability, named NVB-Buffer. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising PJA candidates thanks to providing high endurance, non-volatility, and DRAM-like latency. Despite these advantages, STT-MRAM faces major reliability challenges, i.e. Retention Failure, Read Disturbance, and Write Failure, which have not been addressed in previously suggested NVB-Buffers. In this paper, we first demonstrate that the retention failure is the dominant source of errors in NVB-Buffers as it suffers from... 

Performance and reliability are two prominent factors in the design of data storage systems. To achieve higher performance, recently storage system designers use DynamicDynamic RAMRAM (DRAM)-based buffers. The volatility of DRAM brings up the possibility of data loss and data inconsistency. Thus, a part of the main storage is conventionally used as the journal area to be able of recovering unflushed data pages in the case of power failure. Moreover, periodically flushing buffered data pages to the main storage is a common mechanism to preserve a high level of reliability. This scheme, however, leads to a considerable increase in storage write traffic, which adversely affects the performance.... 

Exponential backoff is an intrinsic feature of MAC-layer standards of most types of ad hoc networks. It leads to random access channels with memory. In this paper we propose a new network coding-based packet forwarding scheme suitable for multiple unicast scenarios in downlink direction of a wireless network. The wireless nodes as well as the access point attempt to access the channel, based on slotted Aloha with exponential backoff. In the proposed scheme we convert multiple unicast scenario to a combination of several anycast and a multicast scenarios. By proposing an open multiclass queueing network, we are able to derive the maximum stable download throughput of the network. The... 

In this paper, we consider a cognitive radio network in which multiple Secondary Users (SUs) contend to access primary network's channels with a random access scheme. Our goal is to analyze SUs' queuing delay performance in terms of mean queue lengths and find a minimum buffer space for which the overflow probability is less than a desired threshold. In general, the considered network can be modeled as a multidimensional Markov chain. However, the enormous state space makes the numerical analysis intractable. Nevertheless, the state space can be reduced to a two-dimensional Markov chain in the symmetric channel condition. By this approach, the optimal contention probability that minimizes... 

The fast growth of battery-operated portable applications has compelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the sub-threshold regime many structures has been proposed adding extra transistors to the conventional 6T-cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is... 

Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this paper proposes an STTRAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bitlines of the tag update more. The SRAM part handles the updates... 

Although the read disturb STT-RAM approximation technique improves performance, it consists of an approximate read plus an approximate write both at the same time. So it may degrade the application Quality of Result (QoR) considerably. On the other hand, the incorrect read decision approximation technique improves power without corrupting the stored data. We adopt an opportunity study for instruction-based distinction of read implementation to take advantage of both of the approximation techniques, while enhancing application’s QoR. We evaluated the proposed method using a set of state of the art benchmarks. The experimental results show that our method allows to increase application’s QoR... 

Although the read disturb spin-transfer torque RAM approximation technique improves performance, it may consist of an approximate read plus an approximate write both at the same time. So it may degrade the application quality of result (QoR) considerably. On the other hand, the incorrect read decision approximation technique improves power without corrupting the stored data. We adopt an opportunity study for instruction-based distinction of read implementation to take advantage of both of the approximation techniques, while enhancing application's QoR. We evaluated the proposed method using a set of state-of-the-art benchmarks. The experimental results show that our method allows to increase... 

In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and... 

Emerging Non-Volatile Memories (NVMs) have promising advantages (e.g., lower idle power, higher density, and non-volatility) over the existing predominant main memory technology, DRAM. Yet, NVMs also have disadvantages (e.g., longer latencies, higher active power, and limited endurance). System architects are therefore examining hybrid DRAM-NVM main memories to enable the advantages of NVMs while avoiding the disadvantages as much as possible. Unfortunately, the hybrid memory design space is very large and complex due to the existence of very different types of NVMs and their rapidly-changing characteristics. Therefore, optimization of performance and lifetime of hybrid memory based... 

In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: They support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of... 

In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: They support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of... 

FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any... 

This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the power and the protection capability of the methods are mentioned and compared with previous work Based on the results of experiments and their analysis, one method is selected as best one. The selected method is much better than previous work e.g., duplication with comparison, triple modular redundancy which impose two and three area and power overheads, respectively. © 2007 IEEE