Sharif Digital Repository

We study the problem of power efficient tracking interval management for distributed target tracking wireless sensor networks (WSNs). We first analyze the performance of a distributed target tracking network with one moving object, using a quantitative mathematical analysis. We show that previously proposed algorithms are efficient only for constant average velocity objects; however, they do not ensure an optimal performance for moving objects with acceleration. Towards an optimal performance, first, we derive a closed-form mathematical expression for the estimation of the minimal achievable power consumption by an optimal adaptive tracking interval management algorithm. This can be used as... 

A multi-band CMOS LC Quadrature Voltage Control Oscillator (QVCO) with minimum power consumption is developed to meet the phase noise and frequency band requirements of RFID, Zigbee and Bluetooth standards. To accomplish the multi-band receiving architecture at low power consumption, current switching technique with optimized cross-coupled transistor sizes has been used. A comprehensive analysis of small signal model for complementary architecture including transistor noise sources and their effects on output phase noise amount has been discussed. Using extracted small signal model, coupled and coupling transistor sizes for minimum power consumption and the least achievable phase noise have... 

Exponential growth of traffic and bandwidth demands in current data center networks requires low-latency high-throughput interconnection networks, considering power consumption. By considering growth of both multicast and unicast applications, power efficient communication becomes one of the main design challenges in today's data center networks. Addressing these demands, optical networks suggest several benefits as well as circumventing most disadvantages of electrical networks. In this paper, we propose an all-optical scalable architecture, named as OMUX, for communicating intra-data centers. This architecture utilizes passive optical devices and enables optical circuit switching without... 

This paper presents a new and efficient formulation for the state estimation (SE) which can be solved in one single shot of computation. The proposed approach adopts line flows and the square of voltage magnitudes as the problem state variable and considers both active and reactive power quantities. The objective function is to minimize the weighted sum of the least square values of measurement residuals. The nonlinearity associated with line losses is left by assuming these values as slack variables. Numerical studies are conducted through two standard networks. In order to compare the performance of the proposed method, the conventional weighted least square (WLS) state estimation with... 

Split-Row technique is proved to be one of the most effective methods to reduce the routing complexity of fully-parallel LDPC decoders. This technique is based on the idea of splitting each check node processor to multiple smaller processors. This paper introduces a new method, to increase the power-efficiency of Split-Row LDPC decoders. The proposed method is called trust to the truthful check node (TTCN), enabling the decoder to only depend on a portion of check node processors at specific decoding iterations. This leads to an average reduction of 30%-40% in the check node dynamic power consumption. This is achieved by means of trust to a minority of check node processors and gating the... 

In this paper, an extended large wireless network, with a single transmitter-receiver pair, under the secrecy constraint is considered. In contrast to works which use idealized assumptions, a more realistic network situation with unknown eavesdroppers locations is investigated: the legitimate users only know their own Channel State Information (CSI), not the eavesdroppers CSI. Also, the network is analyzed by taking in to account the effects of both fading and path loss. Under these assumptions, a power efficient cooperative scheme, named stochastic virtual beamforming, is proposed. Applying this scheme, any desired pair of secure rate and outage level denoted by (Rs, ϵ) will be achievable... 

Mobile portable embedded devices are becoming an integral part of our daily activities in the vision of Internet of Things (IoT). Nevertheless, due to lack of mobility support in the IPv6 routing protocol for low-power and lossy networks (RPLs), which is standardized for multihop IoT infrastructures, providing reliable communications in terms of packet delivery ratio (PDR) in mobile IoT applications has become significantly challenging. While several studies tried to enhance the adaptability of RPL to network dynamics, their utilized routing metrics have prevented them from establishing long-lasting reliable paths. Furthermore, the stochastic parent replacement policy in the standard version... 

Non-volatile memory (NVM) technologies are promising alternatives to traditional CMOS memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in reconfigurable systems such as Field-Programmable Gate Arrays (FPGAs). In this paper, we investigate the applicability of different NVM technologies for the configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). Quantitative analysis for various FPGA architectures using different memory technologies shows the benefits of the proposed scheme  

A 37 dBm power amplifier (PA) is designed on a 0.25 μm optical T-gate pseudomorphic high electron mobility transistor (pHEMT) technology. The design of this two-stage PA along with a step-by-step design procedure is presented in this paper. This methodology can be used for design of PA in different technologies and frequencies. The PA delivers 5 W output power over the frequency band of 13-19 GHz. It shows average power-added efficiency of 37% and large signal gain of 15 dB in measurements which is consistent with simulation results. The output power and efficiency of the realised amplifier reach maximums of 37.6 dBm and 45%, respectively. Considering output power, bandwidth, chip area and... 

This paper introduces an alternative Fault-Tolerant Power-Aware Hybrid Adder (or simply FARHAD). FARHAD is a highly power efficient protection solution against errors in application with high number of additions. FARHAD, similar to earlier studies, relies on performing add operations twice to detect errors. Unlike previous studies, FARHAD uses an aggressive adder to produce the initial outcome and a low-power adder to generate the second outcome, referred to as the checker. FARHAD uses checkpointing, a feature already available to high-performance processors, to recover from errors. FARHAD achieves the high energy-efficiency of timeredundant solutions and the high performance of... 

This paper proposes a power-efficient flow-control method to tackle the problem of crosstalk faults in Network-on-Chips (NoCs). The method, called FRR (Flit Reordering/Rotation), combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a flit sequence which produces the lowest number of OD transitions on NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of... 

Several lower extremity exoskeletal systems have been developed for augmentation purpose. Common actuators, have important drawbacks such as complexity, and poor torque capacities. The main scope of this research is to propose a series elastic actuator for lower extremity exoskeletal system which was designed based on muscle functional analysis. For this purpose, a biomechanical framework consisting of a musculoskeletal model with ten degrees-of-freedom actuated by eighteen Hill-type musculotendon actuators per leg is utilized to perform the muscle functional analysis for common daily human activities. The simulation study illustrated functional differences between flexor and extensor... 

Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM... 

The gas turbine (GT) is known to feature low capital cost to power ratio, high flexibility, high reliability without complexity, short delivery time, early commissioning and commercial operation and fast starting-accelerating. Hence, researchers all over the world are working to increase the output power and efficiency of gas turbine cycle. One of the important techniques to increase the output power of such cycles is the compressor inlet air cooling method. The objective of this paper is to analysis the gas turbine cycle from both energy and exergy point of view. Thus, two important methods for increasing the output power, i.e. fog and media inlet air cooling systems are discussed.... 

Today, the production of energy and electricity is one of the major concerns of mankind. Electricity generation by solar energy is considered as one of the alternatives to fossil fuels. Solar chimneys mechanism is based on a natural phenomenon. In this process the solar energy heat up the earth's surface and the surrounding air. Due to the density difference between cold air and warm air, heated air ascends and causes air circulation. In this study, mathematical modelling of solar chimney and governing equations of this system will be discussed. In order to validate the numerical results, upwind velocity in chimney has been compared with a reliable reference results. As well as, the... 

Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure 109 - 1012 writes per cell, making a nonvolatile cache (NV-cache) with a lifetime of dozens of years under ideal working conditions. However, nonuniformity in writes to different cache lines considerably reduces the NV-cache lifetime to a few months. Writes to cache lines can be made uniformly by wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective wear-leveling technique with... 

Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present a Power gating Switch Box Architecture (PESA) for routing network of SRAM-based FPGAs to overcome the obstacle for further device integration. In the proposed architecture, by exploring various patterns of used multiplexers in switch boxes, we employ a configurable controller to turn off unused... 

Field-Programmable Gate Arrays (FPGAs) employ a significant amount of SRAM cells in order to provide a flexible routing architecture. While this flexibility allows for a rather easy realization of arbitrary functionality, the respectively required cells significantly increase the area and power consumption of the FPGA. At the same time, it can be observed that full routing flexibility is frequently not needed in order to efficiently realize the desired functionality. In this work, we are proposing an FPGA realization which focuses on what is needed and realizes only a subset of the possible routing options using what we call Turn-Restricted Switch-Boxes. While this may yield a slight... 

In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results show that the probability of an SET resulting in a soft error can be reduced up to 90% by choosing a proper delay value. The soft error rate of the SETUR due to SEUs occurring inside the latch is reduced by 95% while having lower area, power and performance overhead than the previously proposed...