Sharif Digital Repository

A 6-bit passive phase shifter for S frequency band has been designed in a standard HEMT technology. A new switched-network topology has been proposed for implementing the 5.625 phase shift step which these digital bits are series with each other. We used Advanced Design System (ADS2010) to perform simulations. These digital bits will produce 64 different mode phase shift of -177.15 to +177.15 degree. In all cases simulation obtained less than 1 % error  

This paper presents the design of a 6-bit active digital phase shifter in 0.18-μm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3±0.9 dBm at 3.5 GHz for overall phase states  

In this paper a 6-bit vector-sum phase shifter with a full 360° variable phase-shift range for S-band has been designed and simulated using standard 180 nm CMOS technology. A new In-phase and Quadrature (I and Q) network to generate quadrature signals with minimum I and Q amplitude mismatch over wide bandwidth is proposed and deployed in the vector sum phase shifter. The designed phase shifter achieves an RMS (root mean square) phase error less than 1.34° and an RMS amplitude error less than 0.43 dB over wide bandwidth of 2 – 4 GHz, resulting in a 6-bit resolution. The gain of phase shifter chain varies from 3 to −6 dB over S-band of 2 – 4 GHz. Moreover the input of phase shifter is widely... 

In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2-4GHz) applications. The designed phase shifter in 180nm CMOS technology achieves an RMS phase error in the range of 0.607-1.18? with -50dBm input signal over 2-4GHz frequency band. With lower input signal of -75dBm, the RMS phase error is 0.621-1.34? for 2-4GHz input frequency. The proposed phase shifter shows an RMS amplitude error... 

The locking of two mutually coupled microwave oscillators is considered. The common frequency of oscillation is obtained both without and in the presence of a non-linear reactance. The effect of the non-linear reactance on the locking bandwidth is studied. It is shown analytically that, unlike the common injection locked oscillator case, the locking bandwidth can be either increased or decreased by the non-linearity. The variations in amplitude of oscillations is investigated. It is demonstrated that the total power delivered by the active devices decreases in interinjection locked oscillators  

An X-band core chip is designed and fabricated in 0.18-μm CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, each of which includes a 6-b phase shifter, a 6-b attenuator, along with two input and output amplifiers. A new architecture for realizing such a core chip system and a low loss circuit for 5.625° phase shift block are proposed. The overall rms phase and gain errors are better than 2° and 0.25 dB, respectively, in both RX/TX paths. The gain of each path is around 12 dB, while the output 1-dB compression point is higher than 10 dBm over the... 

This paper presents a tunable reflection/transmission coefficient (TRTC) circuit based on a 45° hybrid coupler that is potentially useful for leakage cancelation purposes. The analysis of the proposed TRTC circuit shows that the circuit can cover any reflection/transmission coefficient of less than 0.5 on the Smith chart by adjusting only two variable resistors. Meanwhile, the real and imaginary parts of the reflection/transmission coefficient can be tuned independently, facilitating the use of this circuit in feedback systems. To implement the 45° hybrid coupler used in the proposed TRTC circuit, a new wideband planar topology for arbitrary phase and amplitude hybrid coupler is introduced.... 

This paper presents a new implementation of adaptive beamforming algorithm that can be fully implemented on chip. It does not require the knowledge of the incoming signal direction or phase shifter characteristics. Besides, it eliminates the need for the ADC to convert the analog output signal to digital values for the microprocessor and the DAC to apply the calculated values to the control voltages of the analog phase shifters. Thus, it exhibits better convergence speed. In addition, the need for the complex and power-hungry processor is eliminated. Therefore, this implementation consumes less power. Analytical equations and constraints on system design parameters are derived, and the... 

This paper presents a new implementation of adaptive beamforming algorithm that can be fully implemented on chip. It does not require the knowledge of the incoming signal direction or phase shifter characteristics. Besides, it eliminates the need for the ADC to convert the analog output signal to digital values for the microprocessor and the DAC to apply the calculated values to the control voltages of the analog phase shifters. Thus, it exhibits better convergence speed. In addition, the need for the complex and power-hungry processor is eliminated. Therefore, this implementation consumes less power. Analytical equations and constraints on system design parameters are derived, and the... 

This article proposes a tunable composite right-/left-handed transmission line consisting of a transversely magnetized ferrite substrate periodically loaded by microstrip inductors. The gapless transition between the left- and right-handed bands (balanced response) is the main characteristic of this structure. This composite right-/left-handed transmission line is proposed in both reciprocal and nonreciprocal versions. Based on periodic structure analysis, the dispersion relation is estimated theoretically and validated numerically by the finite-element method in the reciprocal case. Theoretical and numerical results demonstrate the tunability of the proposed structures by changing the DC... 

In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively  

Rotating field gradients (RFGs), generated by simultaneously applying sine- and cosine-modulated gradient waveforms along two perpendicular directions, provide an alternative diffusion sensitization mechanism for magnetic resonance imaging and spectroscopy. Two RFGs with a 90-degree phase shift between them are applied around the 180-degree RF pulse in a spin echo sequence to measure the diffusion orientation distribution function (dODF) directly. The technique obviates transforming the data from a space reciprocal to the displacement space. Here, we compare RFG results with those obtained by two pulsed field gradient (PFG) techniques: q-ball imaging (QBI) and its extension to constant solid... 

A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications  

In this paper, a modified method based on the frequency discriminator technique for measuring phase noise of microwave oscillators is presented. In the proposed method, the phase shifter is omitted. In contrast, a 90° hybrid with one more channel containing a phase detector, and a low-noise amplifier is added to the measurement setup. It can be said that an in-phase/quadrature phase-noise detection has been developed. With the proposed method, tuning of the variable phase shifter is not needed anymore. Therefore, the measurement is done automatically, and as a result, the measurement time is decreased. Another considerable advantage of this method is that the method is theoretically... 

The design procedure and measured results of a novel 4 × 4 Butler matrix are presented in this paper. This asymmetrical structure provides fairly flexible phase outputs; therefore, the array radiation pattern can be rotated around the array normal axis. The structure of this modified Butler matrix is discussed in detail, and the explicit design formulas are derived to achieve the arbitrary main beams direction. Using the proposed design procedure, the Butler matrix can provide even broadside and endfire beams. In addition, this structure is employed to design two Butler matrices, which generate similar patterns as a conventional 8 × 8 Butler matrix, using only single layer circuits with... 

This paper presents a highly-linear transceiver core chip for X-band phased-array systems with two RX and one TX channels. Implemented in a standard 0.18-μm CMOS technology, the core chip provides 6-bit phase control (with rms error <2°) and 6-bit gain control (with rms error <0.6 dB) both within the 8.5–11.5 GHz frequency band. Improved accuracy is also available by digital calibration in narrowband applications. The receivers achieve a gain of 13.5 dB, an IIP3 of +10.3 dBm, and a noise figure of 8.2 dB, while drawing 170 mA per channel from the 3.3 V supply. The chip also provides an additional low-gain mode which further enhances IIP3 to +19.1 dBm and the input-referred P1dB to +11.4 dBm.... 

Usually the digital phase shifters are used to steer the beam of a phased array antenna, and the accuracy of beam steering and other properties of the radiation pattern is dependent on the number of bits of the phase shifter and its resolution. In this paper the results of simulations, accomplished using a number of phase feeding methods in order to reduce the phase quantization error effects are presented and three new methods are introduced and compared with the previous works. Copyright 2006 IEICE