Sharif Digital Repository

In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies  

Low noise oscillator design has always been an important subject. Oscillators aren’t usually applicable in free-run mode. Thermal instability and high phase noise level near the carrier frequency are some of the reasons which makes the oscillator not to be used in free-run mode. Using the oscillator in a phase locked loop overcomes the mentioned problems. The oscillator considered in this project, uses a SAW resonator(1GHz). Low phase noise level at far carrier offsets, is the main feature of this oscillator. However, the near carrier phase noise isn’t good enough. Consequently, using a phase locked loop, we lock the oscillator to a low noise and stable source in order to increasing thermal... 

In this thesis first of all we investigate phase noise and it's generation factors. Then we design and implement an ultra low phase noise oscillator. To do this, an ultra low phase noise oscillator which is tunable in 1-2GHz with 100MHz steps will be designed. The outline of the circuit is as follows: at the first we design a VCO which is ultra low phase noise and mechanically tunable in 1-2GHz by means of rotation of a handle. Then a phase locked loop will be built with the help of an ultra low phase noise OCXO at 100MHz and one SPD1 which generates harmonics of OCXO's output frequency. For the next, design and implementation of a 1.6GHz oscillator with fixed output frequency has been done.... 

Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been... 

In this thesis, design and fabrication of wide band frequency synthesizer with low spurious and low phase noise is investigted. It is very important to use an apropriate frequency synthesizer structure which would meet intended properties. In order to reach a low step size and high switching speed, using DDS is recomended; as well as using composition of DDS and PLL in order to meet a low spurious level. The main objective of this thesis is to investigate the best composition of outlet spures; so beside optimization of other properties, the main motivation has been focused on decreasing spures. Moreover, after studying Mechanisms of spures production in DDS outlet, some methods for... 

With the ever-increasing communication need for propagating signals in authorized empty bands, the goal of this thesis is based on finding these unused bands and using them,which called Cognitive Radio. In this project, design and implementation of radio frequency building blocks of a receiver in the UHF band (400 to 800 MHz) is performed. In this project, however, the radio frequency building blocks include low noise amplifier, high-frequency quadrature mixers, high-frequency oscillators, tunable low-pass filter,band select filter,phase-locked loop and synthesizer, all of which are introduced, examined and implemented. Moreover, a new method which mitigates the speed limitation is verified.... 

In this research, the design of a broadband multi-phase frequency synthesizer, applicable for the multi-path structure in the 5G NR1 transmitter, is investigated. This standard presents new challenges for synthesizer design; The synthesizer in such a system must cover a wide frequency range. On the other hand, since this standard employs Orthogonal Frequency Division Multiplexing, it must meet the stringent requirement of integrated phase noise over multiple decades of frequency. The synthesizer employs the phase-locked loop architecture. The frequency division method has been used to construct eight symmetrical phases. The designed synthesizer can generate a frequency range of 600 MHz to 5... 

With the increase of electric energy demand, one of the human concerns is to create the infrastructure for the production and transmission of energy in order to meet this need. Since the network must have the ability to supply the load during the peak load times, practically during the non-peak load times, many production capacities remain unused and their productivity decreases. One of the ways to reduce this problem due to the increase in penetration of batteries in the network can be the participation of battery banks to inject power into the network during peak load times. The goal of this project is to develop an 8 kilowatt-hour battery bank system that can inject 2 kilowatts of power... 

Integration of radio transceivers results in developing low power low cost wireless systems and allows delivery of multimedia contents to battery-powered mobile terminals. Portable reception of digital video for hand-held devices is one of the applications, for which, some telecommunications standards have been developed in the recent years. This research deals with the integrated implementation of the radio frequency parts of the digital video receiver, especially the frequency synthesizer. The key aspects of the digital video reception system are the required signal to noise ratio, which is relatively high, wide band input signals and strong interferers in the receiving band.
In... 

Phase noise is one of the most important parameters in communication systems especially in receivers. Implementation of low phase noise oscillators has always been important.One of the most important parameters in reducing the phase noise of the oscillator is the quality factor of the cavity used in its structure. As a result, increasing the quality factor of the cavity can reduce the oscillation phase noise. Cylindrical waveguides in higher order modes have a higher quality factor than the main modes of excitement. As a result, this property can be used to increase the quality factor of the cavity and reduce the phase noise of the oscillator. This will increase the size of the cavity. The... 

In this thesis, we statistically model and analyze one of the main systems in optical communications which are based on Second HarmonicGeneration (SHG) process. To this end, we first introduce various applications of this process in optical communication systems and see that the main application of this nonlinear process is in the process of optical clock recovery in both of OTDM and SPE_OCDMA networks. In the rest of the thesis, we characterize the mathematical structure of these systems and use that to statistically analyze their behavior. In considering the optical clock recovery system based on SHG, we introduce three intrinsic sources of timing jitter in the system, namely, the On-Off... 

Global Positioning System (GPS) is one of the most widely-used systems nowadays. GPS receivers are frequently integrated along with other communication systems in hand-held devices like cellular phones, tablets and etc. Therefore, implementing receivers with low power consumption (for longer battery lives) and high sensitivity (in order to detect the weak GPS signal) has attracted the attention of many researchers. With the purpose of designing such a low-power and sensitive receiver, we have studied the recently proposed low-power schemes. We have proposed a new architecture for the QLMV Cell; the circuit in which main blocks associated with RF front-end are stacked on top of each other in...