Sharif Digital Repository

We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel architecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been extracted and simulated using NS-2. The results compared with the common used architecture Mesh show that HG has better performance, especially in local traffics and high loads. © IFIP International Federation for Information Processing 2005  

In this study two-dimensional finite element models of Al/SiC metal matrix composites (MMC) by using of ABAQUS Explicit software are investigated. Chip formations and machining forces for three types of MMC with 5, 15 and 20% of SiC reinforcement particles were studied and compared with experimental data. The resulted chips in simulation and the generated chips in experiments have both continuous and saw tooth in appearance. On the other hand, the variation of the cutting forces with the cutting time in simulation and experiment have fluctuating diagram. This is due to the interaction between cutting tool and SiC particles during chip formation. ABAQUS explicit software was used for... 

Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,... 

In recent years, both tissue engineering and microfluidics have significantly contributed in engineering of in vitro skin substitutes to test the penetration of chemicals or to replace damaged skins. Organ-on-chip platforms have been recently inspired by the integration of microfluidics and biomaterials in order to develop physiologically relevant disease models. However, the application of organ-on-chip on the development of skin disease models is still limited and needs to be further developed. The impact of tissue engineering, biomaterials and microfluidic platforms on the development of skin grafts and biomimetic in vitro skin models is reviewed. The integration of tissue engineering and... 

Following Moore's law, the number of transistors on chip has grown exponentially for decades. This growing transistor count, coupled with recent architecture and compiler advances, has resulted in an unprecedented exponential performance increase of computers. With the end of Dennard scaling, however, the power required to operate all transistors at the full performance level simultaneously grows across the technology generations. Consequently, chips will keep an increasing fraction of transistors power gated or dark to remain within the power envelope. The power-gated part of the chip, known as dark silicon, is expected to comprise a significant portion of the die real estate in new... 

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed. Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits. This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects. © 2006 IEEE  

Network-on-Chips (NoCs) employ several virtual channels per input port to mitigate head-of-line blocking issue in transmitting network packets. Unfortunately, these virtual channels are power-hungry resources that significantly contribute to the total power consumption of NoCs. In particular, we make the key observation that even in high load traffic, a number of virtual channels are idle, imposing significant static power overhead. Prior works use power-gating technique to switch off idle VCs and reduce the static power consumption. However, we observe that prior works are mostly suitable for low traffic loads and are ineffective in high traffic loads. In this chapter, we aim to propose a... 

Network-on-Chips (NoCs) consume a significant portion of multiprocessors' total power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power consumption is widely applied to NoCs. However, prior DVS schemes usually impose significant performance overhead to NoCs as NoCs need to work with lower clock frequencies when the supply voltage is scaled down. In this chapter, we propose a novel DVS scheme for NoCs with no performance overhead. We reduce power consumption when there is few Virtual Channels (VCs) that have active allocation requests at each cycle compared to the total number of available VCs. To enable multiple latencies with different slack times, we propose a... 

Network-on-Chips (NoCs) consume a significant portion of multiprocessors' total power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power consumption is widely applied to NoCs. However, prior DVS schemes usually impose significant performance overhead to NoCs as NoCs need to work with lower clock frequencies when the supply voltage is scaled down. In this chapter, we propose a novel DVS scheme for NoCs with no performance overhead. We reduce power consumption when there is few Virtual Channels (VCs) that have active allocation requests at each cycle compared to the total number of available VCs. To enable multiple latencies with different slack times, we propose a... 

Network-on-Chips (NoCs) employ several virtual channels per input port to mitigate head-of-line blocking issue in transmitting network packets. Unfortunately, these virtual channels are power-hungry resources that significantly contribute to the total power consumption of NoCs. In particular, we make the key observation that even in high load traffic, a number of virtual channels are idle, imposing significant static power overhead. Prior works use power-gating technique to switch off idle VCs and reduce the static power consumption. However, we observe that prior works are mostly suitable for low traffic loads and are ineffective in high traffic loads. In this chapter, we aim to propose a... 

This paper presents a reconfigurable network-on-chip (NoC) for many-core chip multiprocessors (CMPs) in the dark silicon era, where a considerable part of high-end chips cannot be powered up due to the power and bandwidth walls. Core specialization, which trades off the cheaper silicon area with energy-efficiency, is a promising solution to the dark silicon challenge. This approach integrates a selection of many diverse application-specific cores into a single many-core chip. Each application then activates those cores that best match its processing requirements. Since active cores may not always form a contiguous active region in the chip, such a partially active many-core CMP requires some... 

Networks on Chip1 have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties 2 which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs to be... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

In this paper, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the arrival order and execution lifetime of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the NoC employed as the communication infrastructure. In this work, we benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application mapped onto disjoint regions (sub-meshes) and then virtually connecting them by bypassing the router pipeline stages of... 

We propose an all-optical arbitration architecture to resolve end-point contention in the optical networks-on-chip. The proposed architecture reduces on-chip optical power and energy losses by 37% and 21%, respectively, compared to Corona's token-based control plane  

In this paper, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the arrival order and execution lifetime of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the NoC employed as the communication infrastructure. In this work, we benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application mapped onto disjoint regions (sub-meshes) and then virtually connecting them by bypassing the router pipeline stages of... 

Chip multiprocessors (CMPs) issue write invalidations (WIs) to assure program correctness. In conventional snoop-based protocols, writers broadcast invalidations to all nodes as soon as possible. In this work we show that this approach, while protecting correctness, is inefficient due to two reasons. First, many of the invalidated blocks are not accessed after invalidation making the invalidation unnecessary. Second, among the invalidated blocks many are not accessed anytime soon, making immediate invalidation unnecessary. While invalidating the first group could be avoided altogether, the second group's invalidation could be delayed without any performance or correctness cost. Accordingly,... 

Core specialization is a promising solution to the dark silicon challenge. This approach trades off the cheaper silicon area with energy-efficiency by integrating a selection of many diverse application-specific cores into a single billion-transistor multicore chip. Each application then activates the subset of cores that best matches its processing requirements. These cores act as a customized application-specific CMP for the application. Such an arrangement of cores requires some special on-chip inter-core communication treatment to efficiently connect active cores. In this paper, we propose a reconfigurable network-on-chip that leverages the routers of the dark portion of the chip to... 

During the recent years, 2D mesh network-onchip has attracted much attention due to its suitability for VLSI implementation. The 2-dimensional de Bruijn topology for network-on-chip is introduced in this paper as an attractive alternative to the popular simple 2D mesh NoC. Its cost is equal to that of the simple 2D mesh but it has a logarithmic diameter. We compare the proposed network and the popular mesh network in terms of power consumption and network performance. Compared to the equal sized simple mesh NoC, the proposed de Bruijn-based network has better performance while consuming less energy. © 2008 IEEE