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Task migration in mesh NOCs over virtual point-to-point connections
, Article 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011, Ayia Napa, 9 February 2011 through 11 February 2011 ; 2011 , Pages 463-469 ; 9780769543284 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
Abstract
Processor allocation in todays many core MPSoCs is a challenging task, especially since the order and requirements of incoming applications are unknown during design stage. To improve network performance, balance the workload across processing cores, or mitigate the effect of hot processing elements in thermal management methodologies, task migration is a method which has attracted much attention in recent years. Runtime task migration was first proposed in multicomputer with load balancing as the major objective. However, specific NoC properties such as limited amount of communication buffers, more sensitivity to implementation complexity, and tight latency and power consumption constraints...
The kautz mesh: a new topology for SoCs
, Article 2008 International SoC Design Conference, ISOCC 2008, Busan, 24 November 2008 through 25 November 2008 ; Volume 1 , 2008 , Pages I300-I303 ; 9781424425990 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
2008
Abstract
Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh topologies, other structures can also be considered especially in 3D VLSI design. The Kautz topology is one of the interconnection architectures for multiprocessors. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the Kautz topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation. ©2008 IEEE
Performance Evaluation of Routing Algorithms in NoCs
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
The increasing complexity of integrated circuits drives the research of new on chip interconnection architectures. Network On Chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Different routing algorithms have been proposed for NoCs such as XY deterministic algorithm, and WF (West First), NL (North Last) and NF (Negative First) as partially adaptive algorithms. OE (Odd Even) is not based on adding virtual channels to network topologies. Unlike previous methods, which rely on prohibiting certain turns in order to achieve...
Modified WK-Recursive Topology for an Optical Network-on-Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of...
Architecture of Reconfigurable Optical Network-on-Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with...
Reducing Power Consumption in NoCs Through Adaptive Data Encoding
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
Recent advances in VLSI technology have led to integrate a few billion transistors on a chip. Systems on Chip provide solutions to the design problems of these systems. As technology scales down to deep sub-micron dimensions, the delay and power consumption of global interconnects become the major bottleneck in SoC design. Networks on Chip (NoCs) have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in large VLSI design. The market trend to mobile digital systems and battery-powered devices add power as a new dimension to VLSI design space in addition to speed and area. Interconnect wires dissipate a significant fraction of power...
Performance Evaluation of Wireless Network-on-Chips
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
On-chip communication infrastructure in chip multiprocessors with large number of processing cores has to be scalable, consumes low power, and provides high bandwidth for hundrededs or even thousands of processing cores. In this project, to this end, the applicability of wireless network technology for on-chip communications in systems with hundreds or thousands of processing elements is investigated. We have combined wired networks (for communication between elements that are close) and wireless networks (for transmition of high volume data flows between cores that are far from each other); so different data flows achive the required bandwidth and point to point delay is reduced. Also, a...
Task migration in mesh NOCs over virtual point-to-point connections
, Article Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011 ; 2011 , p. 463-469 ; ISBN: 9780769543284 ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
Processor allocation in todays many core MPSoCs is a challenging task, especially since the order and requirements of incoming applications are unknown during design stage. To improve network performance, balance the workload across processing cores, or mitigate the effect of hot processing elements in thermal management methodologies, task migration is a method which has attracted much attention in recent years. Runtime task migration was first proposed in multicomputer with load balancing as the major objective. However, specific NoC properties such as limited amount of communication buffers, more sensitivity to implementation complexity, and tight latency and power consumption constraints...
Energy-optimized on-chip networks using reconfigurable shortcut paths
, Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 24 February 2011 through 25 February 2011 ; Volume 6566 LNCS , February , 2011 , Pages 231-242 ; 03029743 (ISSN) ; 9783642191367 (ISBN) ; Modarressi, M ; Tavakkol, A ; Sarbazi Azad, H ; Sharif University of Technology
2011
Abstract
Topology is an important network attribute that greatly affects the power, performance, cost, and design time/effort of NoCs. In this paper, we propose a novel NoC architecture that can exploit the benefits of both application-specific and regular NoC topologies. To this end, a subset of NoC links bypass the router pipeline stages and directly connect remotely located nodes. This results in an NoC which holds both fixed connections between adjacent nodes and long connections virtually connecting non-adjacent nodes. These shortcut paths are constructed at run-time by employing a simple and fast mechanism composed of two processes: on-chip traffic monitoring and path reconfiguration. The...
A novel test strategy and fault-tolerant routing algorithm for NoC routers
, Article Proceedings - 17th CSI International Symposium on Computer Architecture and Digital Systems ; 2013 , Pages 133-136 ; 9781479905621 (ISBN) ; Fallahzadeh, R ; Hessabi, S ; Alirezaie, J ; Computer Society of Iran; IPM ; Sharif University of Technology
IEEE Computer Society
2013
Abstract
In this paper, we present a novel routing algorithm in order to avoid deadlock and packet dropping. In our proposed algorithm the network-on-chip (NoC) is capable of tolerating faults in presence of control faults in combinational parts of routers. In addition, by modifying the functionality of the router, the router is enabled to test its own, as well as the preceding router's functionality based on the routing algorithm, destination address and previous router's situation. Each router recognizes the faulty neighbor and announces it to successive routers. In this scheme no extra packets will be generated. We analyze the effects of our method on latency, power consumption and drop rate. Our...
Analysis, Evaluation and Improving the Performance and Power consumption of Mapping and Scheduling algorithms in Network on Chip
, M.Sc. Thesis Sharif University of Technology ; Vosoughi Vahdat, Bijan (Supervisor) ; Hessabi, Shaahin (Supervisor)
Abstract
According to Moor’s law, the number of transistors per chip would double every 1.5 years. It means that the number of processors, memory and hardware cores available on the chip also increases. In SoC, a number of IP cores and communication links or buses are integrated on a chip. According to inefficiency of the interconnection bus used in SoCs for a large number of processors, NoC has been introduced in the beginning of the current decade. In the NoC paradigm a router-based network is used for packet switched on-chip communication among cores. A typical NoC architecture will provide a scalable communication infrastructure for interconnecting cores. One of the most important features of...
Design and Evaluation of a 3D Network on chip with an Efficient Topology
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
Three dimensional or vertical integration is a new way of increasing the performance and expanding the capabilities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. Using the third dimension, different topologies could be implemented in these chips and positive effects of this integration like decreasing the length of interconnections and decreasing the communication latency as the result of that could be utilized. In addition to common topologies like mesh and torus, it is possible to implement other structures in three dimensional integration. Topologies with lower...
Performance and Power-Efficient Design of Non-Volatile Shared Caches in Multi-Core Systems
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Emerging memory technologies such as STT-RAM, PCM and resistive RAM are probable technologies for caches and main memories of the future multi-core architectures. This is because of their high density, low leakage current and non-volatility. Nevertheless, the overhead of latency and energy consumption of write operation in these technologies are the main open problems. Previous works have suggested various solutions, in architecture and circuit levels, to reduce the writing overheads. In this research, we study the integration of STT-RAM in 3-dimensional multi-core environments; and propose solutions to address the problem of writing overheads when using this technology in cache...
Accelerated FPGA-Based NOC Simulation With Software Configuration
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
To address these challenges, we propose a new...
To address these challenges, we propose a new...
Mapping and Scheduling Applications onto Multi-Core Chip-Multiprocessors in Dark-Silicon Era
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. This concept is the basis of the Dark Silicon definition. To address this issue, it is needed a structure to guaranty Limited power budget and obtain sufficient flexibility and performance for different applications with variety communication needs. Regarding to this structure, our aim is to present a platform for Networks-on-Chip that uses clustering and resource sharing among cores. Moreover, as task mapping on processing elements in NOCs is one of the most effective way to...
Performance Optimization of Cu Wires for Network-on-chip Based Many-core Architectures
, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
The exponential increase in power density within a chip due to higher frequency of operation in recent years (Moor's law) is a major limiting factor for designers. Increasing the number of parallel cores instead of increasing the frequency of operation is a possible solution. The design of connections within the cores can be followed by the old process but the global interconnectsbetween the cores instead of point to point can be replaced byNetwork-on-Chip (NoC). In this thesis, The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of coppe. The optimal...
Task Migration in 3D NoCs Using Game Theory
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
Combination of 3D IC technology and network on chip (NoC) is an effective solution to increase system scalability, and also alleviate the interconnect problem in large scale integrated circuits. However, due to the increased power density in 3D NoC systems and the destructive impact of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. Since hardware thermal control techniques, such as DVFS, can cause significant degradation on chip performance, in this thesis we propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in 3D NoCs. The objective of this...
Design and Implementation of a Run-time Adaptive NoC for Energy Reduction
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shaahin (Supervisor)
Abstract
Network-on-Chip has been introduced as an effective and scalable communication infrastructure for multiprocessor systems. Nowadays, different applications with various traffic patterns and timing demands must be executed on these platforms. However, static NoCs only perform well for specific domain of applications. Therefore, for different applications, parameters of the system should be designed for the worst case scenario that is considered to be executed on it, or for each domain of application, a chip should be fabricated. The first solution leads to underutilization of system resources and the second one imposes cost of refabricating. Consequently, designers have offered different...
Analysis of Router Architecture on Efficiency and Power Consumption of NoCs
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Networks on Chip have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of IP cores (or processing elements) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of chips. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for Network on Chips which allocate a set of Intellectual Properties (IPs) to determined network topologies. In these mapping...
A Novel Fault-Tolerant Routing Algorithm for Networks on Chip
,
M.Sc. Thesis
Sharif University of Technology
;
Sarbazi Azad, Hamid
(Supervisor)
Abstract
Due to the rapid growth of technology, the number of cores on a single chip has increased, caused thousands (or millions) of transistors being tight in a new layout consequently. Technology scaling arise the sensitivity and likelihood of faults. Thus, fault management is one of the important challenging issues in multiple core design we should face. Faults can be permanent, transient, and intermittent. Apart from the fact that how and when a fault occurs, supporting a fault-tolerant or fault-prevention routing is a must in NoCs. To target mentioned problem, we have proposed two routing algorithm in this thesis. The first algorithm is FaulToleReR, which is a reconfigurable fault (faults can...