Sharif Digital Repository

In this paper a new technique called switched-resistor is used as an alternative to switched-capacitor circuits in a low-voltage low-power high-speed A/D converter. Simulation results for an 8-bit 150MS/s pipeline ADC are presented. This converter consumes 20mW from a 1.8V supply and provides an ENOB of 7.5bit. © 2007 IEEE  

this paper presents a new class AB circuit for current-mode signal processing. The proposed circuit provides high-dynamic range, low distortion and accurate definition of quiescent current and it is well suited for high-speed applications. A third-order low-pass filter with a cutoff frequency of 200MHz and 51dB dynamic range is also presented. The Alter consumes 2.7mW from 1.8V supply. © 2007 IEEE  

Flooding algorithm is one of the most significant algorithms used in sensor networks. Although simple, this algorithm causes a large amount of energy and bandwidth to be wasted. The most important application of flooding is RREQ flooding in initial step of most routing algorithms. Although simple, this algorithm causes a large amount of energy and bandwidth to be wasted. Most previous efficient flooding algorithms use location information which is impossible for simple node in sensor network. Some others are not suitable for RREQ flooding due to eliminating redundant retransmissions. We present a modified flooding that simultaneously decreases energy consumption as well as network delay.... 

In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with... 

In this paper, we propose a novel approach to extract a network of half adders from the gate-level net-list of an addition circuit while no internal equivalences exist. The technique begins with a gatelevel net-list and tries to map it into word-level adders based on an efficient bit-level adder representation. It will be shown that the proposed technique is suitable for several gate-level architectures of multipliers, as it extracts adder components in a step-wise method. This approach can also be generalized to other arithmetic circuits. In order to evaluate the effectiveness of our approach, we run it on several arithmetic circuits and compare experimental results with those of... 

The purpose of this paper is to address the question of well-posedness and spectral controllability of the wave equation perturbed by potential on networks which may contain unbounded potentials in the external edges. It has been shown before that in the absence of any potential, there exists an optimal time T∗ (which turns out to be simply twice the sum of all length of the strings of the network) that describes the spectral controllability of the system. We will show that this holds in our case too, i.e., the potentials have no effect on the value of the optimal time T∗. The proof is based on the famous Beurling-Malliavin’s Theorem on the completeness interval of real exponentials and on a... 

The purpose of this paper is to address the question of well-posedness and spectral controllability of the wave equation perturbed by potential on networks which may contain unbounded potentials in the external edges. It has been shown before that in the absence of any potential, there exists an optimal time T∗ (which turns out to be simply twice the sum of all length of the strings of the network) that describes the spectral controllability of the system. We will show that this holds in our case too, i.e., the potentials have no effect on the value of the optimal time T∗. The proof is based on the famous Beurling-Malliavin’s Theorem on the completeness interval of real exponentials and on a... 

One of the important yet insufficiently studied subjects in fair allocation is the externality effect among agents. For a resource allocation problem, externalities imply that the share allocated to an agent may affect the utilities of other agents. In this paper, we conduct a study of fair allocation of indivisible goods when the externalities are not negligible. Inspired by the models in the context of network diffusion, we present a simple and natural model, namely network externalities, to capture the externalities. To evaluate fairness in the network externalities model, we generalize the idea behind the notion of maximin-share (MMS) to achieve a new criterion, namely,... 

The design of a complex active-RC filter for low-IF Wireless applications is described. Fifth-order complex Butterworth filter is designed using Class-AB operational amplifier architecture. This new structure makes the filter suitable for low power applications with high dynamic range. Simulation results show that the filter provides more than 40 dB image rejection ratio (IIR) and dynamic range of 82dB. The complete filter including on-chip tuning circuit consumes only 4.3mW with 1.8V single supply voltage. © 2007 IEEE  

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch... 

We present the results on the correlation between the flux to voltage transfer function, Vspp, of the rf-SQUID and the rf-bias frequency as well as rf-bias power. Measurements were performed for different SQUID gradiometer samples chosen from the same batch or different batches. In order to have full control on the electronics parameters, an experimental rf-SQUID circuit was designed and implemented with an operation frequency of 600 MHz to 900 MHz. According to our findings, It has been observed that at any particular rf-bias power, Vspp vs. rf-bias frequency shows Sine-like behavior. We observed that the main lobe maxima exist close to the resonance frequency of the LC tank circuit and by... 

In this paper, we describe an innovative method to model and solve spatio-temporal behavior of nuclear reactor cores via three-dimensional multilayer cellular neural networks. This method uses electrical elements and the existing duality between neutronic and thermal-hydraulic parameters of nuclear reactors. The relevant electrical circuit can be simulated by existing professional electrical circuit software. This research goes beyond our previous efforts to use a neural computing approach in the nuclear field. Modeling and solving simple nuclear reactor kinetic equations is now expanded to a complete dynamic calculation, integrating the core thermal-hydraulic models and the relevant... 

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between... 

In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1-1.5V and Vth=0-0.8V, are analyzed to find optimal Vdd and Vth BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and... 

Solid State Drives (SSDs) have recently emerged as a high speed random access alternative to classical magnetic disks. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-flash standards to respond to ever increasing application demands. In this paper, we first give a deep look at how different flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement... 

The plausibility of embedding cycles of different lengths in the graphs of a network (known as the pancyclicity property) has important applications in interconnection networks, parallel processing systems, and the implementation of a number of either computational or graph problems such as those used for finding storage schemes of logical data structures, layout of circuits in VLSI, etc. In this paper, we present the sufficient condition of the pancyclicity property of OTIS networks. The OTIS network (also referred to as two-level swapped network) is composed of n clones of an n-node original network constituting its clusters. It has received much attention due to its many favorable... 

Continuous and remote monitoring of vital health-related and physical activity signs of a patient is one of the most important technology-oriented applications to monitor the health-care of ill individuals. In this paper, an innovative framework for a wireless Body Area Network (BAN) system, based on the IEEE 802.15.6 standard, with three types of sensors is proposed and implemented. These include Electrocardiogram (ECG), Force Sensitive Resistor (FSR) and Gyroscope. The proposed design is a novel implementation of an embedded system for the real-time processing and analyzing of the ECG signal, gait phases, and detection of the respiration rate from the ECG signal, by means of small... 

A 2-hued coloring of a graph G is a coloring such that, for every vertex v∈V(G) of degree at least 2, the neighbors of v receive at least two colors. The smallest integer k such that G has a 2-hued coloring with k colors is called the 2-hued chromatic number of G, and is denoted by χ2(G). In this paper, we will show that, if G is a regular graph, then χ2(G)-χ(G)≤2log 2(α(G))+3, and, if G is a graph and δ(G)<2, then χ2(G)-χ(G)≤1+4 Δ2δ-1⌉(1+log 2Δ(G)2Δ(G)-δ(G)(α(G))), and in the general case, if G is a graph, then χ2(G)-χ(G)≤2+min α′(G),α(G)+ω(G)2  

The plausibility of embedding cycles of different lengths in the graphs of a network (known as the pancyclicity property) has important applications in interconnection networks, parallel processing systems, and the implementation of a number of either computational or graph problems such as those used for finding storage schemes of logical data structures, layout of circuits in VLSI, etc. In this paper, we present the sufficient condition of the pancyclicity property of OTIS networks. The OTIS network (also referred to as two-level swapped network) is composed of n clones of an n-node original network constituting its clusters. It has received much attention due to its many favorable... 

Wireless ad hoc networks are vulnerable against many types of attacks including black hole. In this paper we investigate the effect of this attack on ad hoc networks. Furthermore, we use hash chain to prevent this type of attack in a network that uses AODV as a routing protocol and results of applying this method has been investigated. Simulation results using OPNET simulator indicates that packet delivery ratio, in the presence of malicious nodes, reduces remarkably and proposed approach can prevent the effect of black hole attacks