Sharif Digital Repository

Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign-sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed... 

The aim of the Software Product Line (SPL) approach is to improve the software development process by producing software products that match the stakeholders' requirements. One of the important topics in SPLs is the feature model (FM) configuration process. The purpose of configuration here is to select and remove specific features from the FM in order to produce the required software product. At the same time, detection of differences between application's requirements and the available capabilities of the implementation platform is a major concern of application requirements engineering. It is possible that the implementation of the selected features of FM needs certain software and... 

This paper presents an efficient way of implementing Taylor expansion Diagrams (TED) that is called Binary Taylor Diagrams (BTD). BTD is based on Taylor series like TED, but uses a binary data structure. So BTD functions are simpler than those of TED. © 2005 IEEE  

The Necklace Hypecube has been recently proposed as an attractive topology for multicomputers and was shown to have many desirable properties such as well-scalability and suitability for VLSI implementation. This paper introduces a parallel algorithm for computing an N-point Lagrange interpolation on a necklace hypercube multiprocessor. This algorithm consists of 3 phases: initialization, main and final. There is no computation in the initialization phase. The main phase consists of [E/2] steps (with E being the number of edges of the network), each consisting of 4 multiplications and 4 subtractions, and an additional step including 1 division and 1 multiplication. Communication in the main... 

Fuzzy inference systems always suffer from the lack of efficient structures or platforms for their hardware implementation. In this paper, we tried to overcome this difficulty by proposing a new method for the implementation of the fuzzy rule-based inference systems. To achieve this goal, we have designed a multi-layer neuro-fuzzy computing system based on the memristor crossbar structure by introducing a new concept called the fuzzy minterm. Although many applications can be realized through the use of our proposed system, in this study we only show how the fuzzy XOR function can be constructed and how it can be used to extract edges from grayscale images. One main advantage of our... 

TQM is a set of management practices throughout the organisation, geared to ensure the organisation consistently meets or exceeds customer requirements. This research tries to investigate the most important barriers to successful TQM implementation in Iranian manufacturing organisations. The authors have studied samples of manufacturing organisations, comprising those that have invested on TQM after the end of March 2009 and were located in Iran. This descriptive and cross-sectional research is carried out via two questionnaires - general questionnaire for success of TQM principles and specific questionnaire for barriers to successful TQM implementation. The statistical population of this... 

In this Paper, a software-based control flow checking technique called SWTES (Software-based error detection Technique using Encoded Signatures) is presented and evaluated. This technique is processor independent and can be applied to any kind of processors and microcontrollers. To implement this technique, the program is partitioned to a set of blocks and the encoded signatures are assigned during the compile time. In the run-time, the signatures are compared with the expected ones by a monitoring routine. The proposed technique is experimentally evaluated on an ATMEL MCS51 microcontroller using Software Implemented Fault Injection (SWIFI). The results show that this technique detects about... 

A new architecture for analog sampled-data filters is presented. This architecture is based on implementing the difference equation of the filter using a neural network. It results in lower sensitivity of filter coefficients to hardware nonidealities. Different tradeoffs in the hardware implementation of the filter are discussed. A design example is also presented. © 2005 IEEE  

In this paper, we present an MPEG-2 video decoder implemented in our ODYSSEY design methodology. We start with an ASIP tailored to the JPEG decompression algorithm. We extend that ASIP by required software routines such that the extended ASIP can now perform MPEG2 decoding while still benefiting from hardware units common between JPEG and MPEG2. This demonstrates the ability of our approach in extending an already manufactured ASIP, which was tailored to a given application, such that it implements new, yet related applications. The implementation platform is a VirtexII-Pro FPGA. The hardware part is implemented in VHDL, and the software runs on a PowerPC processor. Experimental results show... 

In this paper, we propose a new modular topology for interconnection networks, the Recursive Transpose-Connected Cycles (RTCC). The RTCC has a recursive definition quite similar to that of fractal graphs having interesting topological characteristics, making it suitable for utilization as the base topology of large-scale multicomputer interconnection networks. We study important properties of this topology such as diameter, bisection width and issues related to implementation, such as routing algorithms and the average message latency under VLSI layout constraints. In addition, we prove that the RTCC is a Hamiltonian graph, We conclude that, insight of most of the above-mentioned properties,... 

The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

This study investigates the use of structural similarity index (SSIM) on the minimised side effect to image watermarking. For the fast implementation and more compatibility with the standard discrete cosine transform (DCT)-based codecs, watermark insertion is carried out on the DCT coefficients and hence an SSIM model for DCT-based watermarking is developed. For faster implementation, the SSIM index is maximised over independent 4 × 4 non-overlapped blocks, but the disparity between the adjacent blocks reduces the overall image quality. This problem is resolved through optimisation of overlapped blocks, but, the higher image quality is achieved at a cost of high computational complexity. To... 

This paper is aimed at proposing a current based vector control model of the brushless doubly fed induction generator, modelling the presented control method, as well as implementing the proposed algorithm by DSP. In order to achieve the purpose, by presenting a detailed coupled circuit model of BDFIG, the vector model and then the current based vector control algorithm of the mentioned machine are acquired. The way of independent control of torque and power, and also the structure of speed controller amongst the proposed control model are discussed. Additionally, the concepts behind the proposed structure of the speed control system and the way of determining the model parameters are... 

Continuous and remote monitoring of vital health-related and physical activity signs of a patient is one of the most important technology-oriented applications to monitor the health-care of ill individuals. In this paper, an innovative framework for a wireless Body Area Network (BAN) system, based on the IEEE 802.15.6 standard, with three types of sensors is proposed and implemented. These include Electrocardiogram (ECG), Force Sensitive Resistor (FSR) and Gyroscope. The proposed design is a novel implementation of an embedded system for the real-time processing and analyzing of the ECG signal, gait phases, and detection of the respiration rate from the ECG signal, by means of small... 

Enterprise Resource Planning systems (ERP) play a significant role in the management of businesses processes. Determining the influential factors that are positioned behind a successful ERP implementation is critical to gain the most value-added from competitive potentials of such systems. The driver of current research is to gain a deeper understanding of the various subjective criteria to measure ERP implementation success with the aim of enhancing the chance success through investigating ERP implementation performance indicators. By exploring the international literature, a comprehensive list of potential success factors of ERP systems is identified which are complementary and critical to... 

In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA... 

The elliptic curve cryptography (ECC) has gained attention mainly due to its lower complexity compared to other asymmetric methods while providing the same security level. The most performance critical operation in ECC is the point multiplication. Thus, its efficient implementation is desirable. One of the most secure and lightweight ECC curves, which satisfies all standard security criteria, is the Curve25519. In this paper, a low latency Karatsuba-Ofman-based field multiplier (KOM) and an efficient point multiplication over Curve25519 have been proposed. The improvements have been achieved mainly due to the proposed low latency pipelined KOM and efficient scheduling of field operations....