Loading...
Search for: field-programmable-gate-array
0.007 seconds
Total 180 records

    Design and Simulation of Dust Control System in the Air with the FPGA

    , M.Sc. Thesis Sharif University of Technology Ghafouri, Rasool (Author) ; Vosoughi Vahdat, Bijan (Supervisor) ; Hashemi, Matin (Co-Advisor)

    Six-leg AC-AC fault tolerant converter with reduced extra-sensor number

    , Article International Review of Electrical Engineering ; Volume 6, Issue 1 , 2011 , Pages 132-138 ; 18276660 (ISSN) Shahbazi, M ; Poure, P ; Zolghadri, M. R ; Saadate, S ; Sharif University of Technology
    Abstract
    In order to prevent further damage and to provide the continuity of service of six-leg converter in case of open-switch fault, it is mandatory to perform fast fault detection and converter reconfiguration schemes. Extra sensors are needed to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A six-leg fault tolerant converter topology without redundancy and with bidirectional power flow is studied. First simulations are carried out to evaluate the proposed fault detection principle and the fault tolerant converter topology. The fully digital control and the fault detection are... 

    Introduction to emerging SRAM-Based FPGA architectures in dark silicon Era

    , Article Advances in Computers ; Volume 110 , 2018 , Pages 259-294 ; 00652458 (ISSN); 9780128153581 (ISBN) Seifoori, Z ; Ebrahimi, Z ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    Academic Press Inc  2018
    Abstract
    The increased leakage power of deep-nano technologies in the one hand, and exponential growth in the number of transistors in a given die particularly in Field-Programmable Gate Arrays (FPGAs) have resulted in an intensified rate of static power dissipation as well as power density. This ever-increasing static power consumption acts as a power wall to further integration of transistors and has caused the breakdown of Dennard scaling. To meet the available power budget and preclude reliability challenges associated with high power density, designers are obligated to restrict the active percentage of the chip by powering off a selective fraction of silicon die, referred to as Dark Silicon.... 

    Hardware Implementation of Li-Fi System

    , M.Sc. Thesis Sharif University of Technology Sadeghi, Maryam (Author) ; Shabani, Mahdi (Supervisor) ; Kavehvash, Zahra (Co-Supervisor)
    Abstract
    Today, the “wireless” is used almost synonymously with radio-frequency (RF) technologies as a result of the wide-scale deployment and utilization of wireless RF devices and systems. The RF band ranges from 300 kHz to 300 GHz and its use is regulated by regional and international agencies. With the ever-growing popularity of data-heavy wireless communications, wireless products and services, the demand for RF spectrum is outstripping supply, which causes the spectrum congestion. Therefore, the time has come to seriously consider other viable options for wireless communication using the upper parts of the electromagnetic spectrum. In this way, the optical band which includes infrared, visible,... 

    Fault-resilient lightweight cryptographic block ciphers for secure embedded systems

    , Article IEEE Embedded Systems Letters ; Vol. 6, issue. 4 , 2014 , pp. 89-92 ; ISSN: 19430663 Mozaffari Kermani, M ; Tian, K ; Azarderakhsh, R ; Bayat Sarmadi, S ; Sharif University of Technology
    Abstract
    The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

    Design of FPGA Cluster Platform For Cryptanalysis Applications

    , M.Sc. Thesis Sharif University of Technology Hosseini, Hamid Reza (Author) ; Jahangir, Amir Hossein (Supervisor)
    Abstract
    Daily improvements in technology and exchanging important information via internet and connection networks make data and connection security a significant problem. Cryptology is the branch of knowledge which concerns secret communications in all of its aspects. Two major areas of cryptology are cryptography and cryptanalysis. Cryptography is a branch of cryptology concerned with protecting communications from being read by unauthorized people.
    Cryptologists design and create algorithms to improve cryptography along with finding methods to crack those algorithms. Cryptanalysis is a branch of cryptology concerned with cracking the cryptographic systems used by others.
    Cryptographic... 

    Accelerated FPGA-Based NOC Simulation With Software Configuration

    , M.Sc. Thesis Sharif University of Technology Mardani Kamali, Hadi (Author) ; Hesabi, Shahin (Supervisor)
    Abstract
    ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
    To address these challenges, we propose a new... 

    CAD-directed SEU susceptibility reduction in FPGA circuits designs

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 3675-3678 ; 02714310 (ISSN) Zarand, H. R ; Miremadi, S. G ; Pradhan, D. K ; Mathew, J ; Sharif University of Technology
    2007
    Abstract
    This paper presents a SEU-mitigative placement and route of circuits in the FPGAs which is based on the popular placement and route tool The tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation and no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. We have investigated the effect of this tool on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 22%. However, it increases critical path delay and... 

    Fast SEU detection and correction in LUT configuration bits of sram-based FPGAs

    , Article 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007 ; 2007 ; 1424409101 (ISBN); 9781424409105 (ISBN) Zarandi, H.R ; Miremadi, S. G ; Argyrides, C ; Pradhan, D. K ; Sharif University of Technology
    2007
    Abstract
    FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any... 

    CLB-based detection and correction of bit-flip faults in SRAM-based FPGAs

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 3696-3699 ; 02714310 (ISSN) Zarandi, H. R ; Miremadi, S. G ; Argyrides, C ; Pradhan, D. K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2007
    Abstract
    This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the power and the protection capability of the methods are mentioned and compared with previous work Based on the results of experiments and their analysis, one method is selected as best one. The selected method is much better than previous work e.g., duplication with comparison, triple modular redundancy which impose two and three area and power overheads, respectively. © 2007 IEEE  

    Theoretical investigation of the stability of the modes in an array of coupled oscillators for linear and circular arrangements

    , Article 2005 European Conference on Circuit Theory and Design, Cork, 28 August 2005 through 2 September 2005 ; Volume 2 , 2005 , Pages 23-26 ; 0780390660 (ISBN); 9780780390669 (ISBN) Banai, A ; Farzaneh, F ; Sharif University of Technology
    2005
    Abstract
    In this paper an array of N weakly coupled oscillators Is considered. The stability of the main mode (In phase mode) In linear arrangement of oscillators has been proven and the Instability of other modes In this configuration Is demonstrated. For circular arrangement It Is shown that other stable modes may exist If N Is greater than 5  

    A new pipeline implementation of an adaptive IIR filter for noise reduction application

    , Article IEEE International Symposium on Communications and Information Technologies: Smart Info-Media Systems, ISCIT 2004, Sapporo, 26 October 2004 through 29 October 2004 ; Volume 1 , 2004 , Pages 577-581 ; 0780385934 (ISBN) Golmohammadi, A ; Manzuri, M. T ; Ayat, S ; Sharif University of Technology
    2004
    Abstract
    the parallel form in adaptive HR filtering is an efficient realization that provides robust stability monitoring with less complexity than that of the direct form. This paper presents an implementation of two line parallel structure employing a real orthogonal transform and real coefficients second-order section as sub filters on FPGA. Architecture that is implemented is in pipeline fashion and it is independent from its building blocks and they may have its own implementation or in other system numbering. In the last section, we compared throughput of our architecture with a Ti DSP (TMS320C3x/4x), the results show that this architecture works better than the DSP  

    Implementation of the Digital Part of DVB-T Protocol with Reduced Power and Area

    , M.Sc. Thesis Sharif University of Technology Mozafari, Hassan (Author) ; Hessabi, Shaahin (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for... 

    Design and Implementation of 2.5 Gbps Circuit Switching Fabric

    , M.Sc. Thesis Sharif University of Technology Jahani, Sohrab (Author) ; Pakravan, Mohammad Reza (Supervisor) ; Movahhedy, Mohammad Reza (Supervisor)
    Abstract
    Providing high bandwidth network infrastructures for ever increasing need of data transport is of great importance. The underling infrastructure for many communication services such as GSM/3G/4G mobile networks and Internet services is Synchronous Digital Hierarchy (SDH) optical transport systems. SDH are standardized protocols that multiplex multiple lower rate digital bit streams, such as E1 and Ethernet, and transfer them synchronously over optical fiber using lasers or LEDs. In addition to high data transfer rates, flexible network management and protection mechanisms have great importance, hence are part of SDH standards. In order to obtain flexible network architecture and protected... 

    System Level Modeling and Optimization of Accelerator-CPU Communication in Data Centers

    , M.Sc. Thesis Sharif University of Technology Haji Ali Khamseh, Amir (Author) ; Goudarzi, Maziar (Supervisor)
    Abstract
    Due to the data centers rapid growth and introduction of a new basic type of massive data processing platforms which requires accelerators to speedup computation and enhance the efficiency and reduce power consumption, using accelerators is inevitable. Communication and data transfer time between software and hardware is the most of time spent on the use of accelerators. By optimizing this part of the hardware / software platform, we have achieved substantial results in this area. The aim of our study is to organize a survey of real accelerator characteristics. To figure out its defects and main drawbacks, in addition to improving the overall efficiency of system. The implementation of... 

    Designing a 32-Bit Fault-Tolerant ALU Using EDAC

    , M.Sc. Thesis Sharif University of Technology (Author) ; Vosughi Vahdat, Bijan (Supervisor) ; Mortazavi, Mohammad (Supervisor)
    Abstract

    Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since... 

    An Efficient Reconfigurable Architecture in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tamimi, Sajjad (Author) ; Asadi, Hossein (Supervisor)
    Abstract
    Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, Field-Programmable Gate Arrays (FPGAs) are used in industry for implementing either an entire embedded system or a Hardware Description Language (HDL)-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors. In this thesis, we present an efficient reconfigurable architecture to implement embedded processors in... 

    Accelerating Network Firewalls

    , M.Sc. Thesis Sharif University of Technology Milanian, Zhaleh (Author) ; Goudarzi, Maziar (Supervisor)
    Abstract
    With the proliferation of Internet-based applications and malicious attacks, security has become one of the most influential aspects in the network and, it should be considered from the beginning steps of designing the network infrastructure. Based on the fact that pattern matching is considered as one of the most important roles of security devices or applications, it becomes an important procedure in firewalls that have been classified as security equipments which adopt a security mechanism in order to restrict the traffic exchanged between networks and particular users or certain applications. While the trend of using compressed traffic is drastically increasing, this type of traffic is... 

    FPGA-based Fault Injection for Evaluating the Fault Tolerance of Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Mohammadi, Abbas (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

    Design of Fault-tolerance Mechanisms for Soft Multiprocessors

    , M.Sc. Thesis Sharif University of Technology Zabihi, Masoumeh (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract
    Increasing complexity of embedded systems and the need for more computation powerhave directed designers toward using of multiprocessors. SRAM-based FPGAs are suitable platforms for implementation of multiprocessors due to thier low cost, fast time-to-market and re-configurability. FPGA-based multiprocessors are known as soft multiprocessors. The large area of SRAM-based FPGAs is occupied by configuration bits. Configuration bits are vulnerable to high energy particles that can lead to soft errors. In this regards, it is of decisive importance to protect soft multiprocessors against soft errors. This thesis proposes a fault-tolerant method for soft multiprocessors that can detect and...