Sharif Digital Repository

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer... 

Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture... 

This paper introduces a new class of interconnection networks named Star-Pyramid, SP(n). A star-pyramid of dimension n is formed by piling up star graphs of dimensions 1 to n in a hierarchy, connecting any node in each i-dimensional star, 1< i ≤ n, to a node in (i - 1)-star whose index is reached by removing the i symbol from the index of the former node in the i-star graph. Having extracted the properties of the new topology, featuring topological properties, a simple routing algorithm and Hamiltonicity then we compare the network properties of the proposed topology and the well-known pyramid topology. We show that the star-pyramid is more fault-tolerant and has less network diameter than... 

In this paper we have presented a hardware implementation of 32-bit Fault-tolerant ALU (Arithmetic and Logic Unit) which is compared with the current techniques, Residue code, Triple Modular Redundancy (TMR) with single voting and TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA (Field Programmable Gate Array). The new implementation of ALU employing BCH code on Spartan-3 FPGA has been provided. The results show that our fault tolerant method has the lowest hardware overhead and it can correct any 5-bit error in any... 

This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This Scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection... 

In this paper, using of fault tolerant techniques are studied and experimented in speech recognition systems to make these systems robust to noise. Recognizer redundancy is implemented to utilize the strengths of several recognition methods that each one has acceptable performance in a specific condition. Duplication-with-comparison and NMR methods are experimented with majority and plurality voting on a telephony Persian speech-enabled IVR system. Results of evaluations present two promising outcomes, first, it improves the performance considerably; second, it enables us to detect the outputs with low confidence. © 2008 IEEE  

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch... 

A wireless sensor network with a large number of small sensor nodes can be used as an effective tool for gathering data in various situations. Energy is a critical resource in wireless sensor networks and system lifetime needs to be prolonged through the use of energy-aware strategies during system operation. Routing protocols in WSNs might differ depending on the application and network architecture. Many routing protocols have been specifically designed for WSNs where energy awareness is an essential design issue. The aim of this paper is to evaluate the efficiency of a routing protocol named directed flooding which is a fault-tolerant and energy efficient routing protocol for wireless... 

Current massively parallel systems are often composed of hundreds or thousand of components (such as routers, channels and connectors) that collectively possess failure rates higher than what arise in the ordinary systems. Therefore, these systems are required to he equipped with fault-tolerant mechanisms to ensure that the system will keep running in a degraded made until the failed component in repaired. Normally, the faulty components are coalesced into fault regions which may be classified into two major categories: convex and concave regions. In this paper, we propose the first general solution to calculate the probability of occurrences of common fault patterns in torus networks which... 

In this paper we describe two differential fault attack techniques against Advanced Encryption Standard (AES). We propose two models for fault occurrence; we could find all 128 bits of key using one of them and only 6 faulty ciphertexts. We need approximately 1500 faulty ciphertexts to discover the key with the other fault model. Union of these models covers all faults that can occur in the 9th round of encryption algorithm of AES-128 cryptosystem, One of main advantage of proposed fault models is that any fault in the AES encryption from start (AddRoundKey with the main key before the first round) to MixColumns function of 9th round can be modeled with one of our fault models. These models... 

Parallel computers, such as multiprocessors system-on-chip (Mp-SoCs), multicomputers and cluster computers, are consisting of hundreds or thousands multiple processing units and components (such as routers, channels and connectors) connected via some interconnection network that collectively may undergo high failure rates. Therefore, these systems are required to be equipped with fault-tolerant mechanisms to ensure that the system will keep running in a degraded mode. Normally, the faulty components are coalesced into fault regions, which are classified into two major categories: convex and concave regions. In this paper, we propose the first solution to calculate the probability of... 

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI).... 

This paper scrutinizes faults in a CAN controller that may result in masquerade failures, and suggests an even parity mechanism to detect them with minimum hardware overhead. To do this, a CAN controller is modeled by VHDL at behavioral level and is exploited to setup a CAN-based network composed of two nodes. A total of 5,500 faults are injected into essential parts of one of the controllers. The results show that about 3.44% of faults terminate in masquerade failures. The results, also, show that Register bank in the CAN controller are the most sensitive portions in which 92.10% of faults occurring in the Register bank result in masquerade failures. The even parity mechanism detects about... 

This paper analyzes the problem of transient-error recovery of several protecting techniques used in fault-tolerant cache memories. In this paper, reliability and mean-time-to-failure (MTTF) equations for several protecting techniques are derived and estimated. The results of the considered techniques are compared with those of cache memories without redundancies and with only parity codes in both tag and data arrays of caches. Depending on the error rate under which a cache memory will operate, and the size of the cache memory, one of the analyzed cases could be used. If the transient-error rate is very small or the size of cache memory is relatively small, then a protected with only single... 

Flooding technique is widely using to manipulate sensor network essential activities such as synchronization, data gathering, network query and in-network information processing. Reliable and low latency data broadcasting is the primary goal in design of appropriate quality of service aware flooding algorithm. This paper proposes a new error-rate adaptive reliable data flooding strategy. Energy consumption which it the main limitation in sensor network, has been considered in optimal presented scheme. Also the tradeoff between reliability, power consumption and latency has been cared to achieve the finest devise. The simulation results have shown significant enhancement in quality of data... 

Many theoretical studies have compared the hypercube and star graphs from a graph theoretical viewpoint, under structural and algorithmic properties. None of these studies have, however, considered real working conditions and implementation constraints. In this paper, the hypercube and star graphs are compared in view of fault tolerance and technological implementation constraints. In order to realize a fair comparison, we use the unsafely-vector fault tolerant routing algorithm, recently introduced in [1] and [2], for the hypercube and star graph. Under two implementation constraints, namely constant bisection bandwidth and constant node pin-out, we have compared the performance of the two... 

This paper introduces an analytical method for approximating the performance of a soft real-time system modeled by a single-server queue. The service discipline in the queue is earliest-deadline-first (EDF), which is an optimal scheduling policy. Real-time jobs with exponentially distributed deadlines arrive according to a Poisson process. All jobs have deadlines until the end of service and are served non-preemptively. Occurrences of transient faults in the server are also taken into account. The important performance measure to calculate is the loss probability due to deadline misses and/or transient faults. The system is approximated by a Markovian model in the long run. A key parameter,... 

Wireless sensor networks consist of small nodes with sensing, computation, and wireless communicationr capabilities. Many routing protocols have been specifically designed for WSNs where energy awareness is an essential design issue. Routing protocols in WSNs might differ depending on the application and network architecture. In this article, a fault-tolerant and energy efficient routing protocol for wireless sensor networks is proposed This protocol is called Directed Flooding, and is a descendant of the Flooding routing protocol, which consumes less energy, while maintaining high levels of fault-tolerance. This is done by Tending data in a specific aperture instead of broadcasting, which... 

The size and speed of SRAM caches of embedded systems are increasing in response to demands for higher performance. However, the SRAM caches are vulnerable to soft errors originated from energetic nuclear particles or electrical sources. This paper proposes a new protected cache scheme, which provides high performance as well as high fault detection coverage. In this scheme, the cache space is divided into sets of different sizes. Here, the length of tag fields associated to each set is unique and is different from the other sets. The other remained bits of tags are used for protecting the tag using a fault detection scheme e.g., generalized parity. This leads to protect the cache without... 

This paper presents the performance analysis of several best-known partitioning scheduling algorithms in real-time and fault-tolerant multiprocessor systems. To do this, multiple versions of tasks are executed on different processors. Both static and dynamic scheduling algorithms are analyzed. In the case of static scheduling algorithms, rate-monotonic (RM) scheduling policy is considered. In the dynamic scheduling algorithms, the scheduling policies are rate-monotonic and earliest-deadline-first (EDF). Partitioning scheduling algorithms which are studied here are heuristic algorithms that are formed by combining any of the bin-packing algorithms with any of the schedulability conditions for...