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    LTR: A low-overhead and reliable routing for network on chips

    , Article 2008 International SoC Design Conference, ISOCC 2008, Busan, 24 November 2008 through 25 November 2008 ; Volume 1 , Volume 1 , 2008 , Pages 129-133 ; 9781424425990 (ISBN) Patooghy, A ; Miremadi, S. G ; Sharif University of Technology
    IEEE Computer Society  2008
    Abstract
    A fault tolerant routing algorithm is presented in this paper. proposed routing algorithm is based on making a redundant of each packet as well as sending the redundant packets the paths with low traffic loads. Since two copies of each reach the destination node, the erroneous packets are and replaced with the correct ones. To effectively use paths with lower traffic loads, the redundant packets are according to YX routing while the original packets are according to Duato's routing algorithm. Minimizing the of sent redundant packets and exploiting different paths sending the original and redundant packets enable the algorithm to improve the reliability of NoCs with power and performance... 

    Power and performance efficient partial circuits in packet-switched networks-on-chip

    , Article Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013 ; 27 February - 1 March , 2013 , pp. 509-513 ; Print ISBN: 9781467353212 Teimouri, N ; Modarressi, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

    Power and performance efficient partial circuits in packet-switched networks-on-chip

    , Article Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013 ; February , 2013 , Pages 509-513 ; 9780769549392 (ISBN) Teimouri, N ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
    2013
    Abstract
    In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

    A composite-metric based path selection technique for the Tor anonymity network

    , Article Journal of Systems and Software ; Volume 103 , 2015 , Pages 53-61 ; 01641212 (ISSN) Momeni Milajerdi, S ; Kharrazi, M ; Sharif University of Technology
    Abstract
    The Tor anonymous network has become quite popular with regular users on the Internet. In the Tor network, an anonymous path is created by selecting three relays through which the connection is redirected. Nevertheless, as the number of Tor users has increased substantially in recent years, the algorithm with which the relays are selected affects the performance provided by the Tor network. More importantly as the performance suffers, users will leave the network, resulting in a lower anonymity set and in turn lower security provided by Tor network. In this paper, we proposed an algorithm for improving performance and security of the Tor network, by employing a combination of different... 

    Heterogeneous interconnect for low-power snoop-based chip multiprocessors

    , Article Journal of Low Power Electronics ; Volume 8, Issue 5 , 2012 , Pages 624-635 ; 15461998 (ISSN) Shahidi, N ; Shafiee, A ; Baniasadi, A ; Sharif University of Technology
    Abstract
    In this work we propose using heterogeneous interconnects in power-aware chip multiprocessors (also referred to as Helia). Helia improves energy efficiency in snoop-based chip multiprocessors as it eliminates unnecessary activities in both interconnect and cache. This is achieved by using innovative snoop filtering mechanisms coupled with wire management techniques. Our optimizations rely on the observation that a high percentage of cache mismatches could be detected by utilizing a small subset but highly informative portion of the tag bits. Helia comes in two variations: source-based (S-Helia) and destination-based (D-Helia). S-Helia relies on a global snapshot of remote caches collected in... 

    An efficient dynamically reconfigurable on-chip network architecture

    , Article Proceedings - Design Automation Conference, 13 June 2010 through 18 June 2010 ; June , 2010 , Pages 166-169 ; 0738100X (ISSN) ; 9781450300025 (ISBN) Modarressi, M ; Sarbazi Azad, H ; Tavakkol, A ; Sharif University of Technology
    Abstract
    In this paper, we present a reconfigurable architecture for NoCs on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications at run-time. The run-time topology construction mechanism involves monitoring the network traffic and changing the inter-node connections in order to reduce the number of intermediate routers between the source and destination nodes of heavy communication flows. This mechanism should also preserve the NoC connectivity. In this paper, we first introduce the proposed reconfigurable topology and then address the problem of run-time topology reconfiguration.... 

    XYX: a power & performance efficient fault-tolerant routing algorithm for network on chip

    , Article Proceedings of the 17th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2009, 18 February 2009 through 20 February 2009, Weimar ; 2009 , Pages 245-251 ; 9780769535449 (ISBN) Patooghy, A ; Miremadi, G ; Sharif University of Technology
    2009
    Abstract
    Reliability is one of the main concerns in the design of network on chips due to the use of deep-sub micron technologies in fabrication of such products. This paper proposes a fault-tolerant routing algorithm called XYX which is based on sending redundant packets through the paths with lower traffic loads. The XYX routing algorithm makes a redundant copy of each packet at the source node and exploits two different routing algorithms to route the original and the redundant packets. Since two copies of each packet reach the destination node, the erroneous packet is detected and replaced with the correct one. Due to the use of paths with lower traffic rates for sending redundant packets and... 

    An iterative stochastic algorithm based on distributed learning automata for finding the stochastic shortest path in stochastic graphs

    , Article Journal of Supercomputing ; Volume 76, Issue 7 , 2020 , Pages 5540-5562 Beigy, H ; Meybodi, M. R ; Sharif University of Technology
    Springer  2020
    Abstract
    In this paper, we study the problem of finding the shortest path in stochastic graphs and propose an iterative algorithm for solving it. This algorithm is based on distributed learning automata (DLA), and its objective is to use a DLA for finding the shortest path from the given source node to the given destination node whose weight is minimal in expected sense. At each stage of this algorithm, DLA specifies edges needed to be sampled. We show that the given algorithm finds the shortest path with minimum expected weight in stochastic graphs with high probability which can be close to unity as much as possible. We compare the given algorithm with some distributed learning automata-based... 

    Solving stochastic path problem: particle swarm optimization approach

    , Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 18 June 2008 through 20 June 2008, Wroclaw ; Volume 5027 LNAI , 2008 , Pages 590-600 ; 03029743 (ISSN); 354069045X (ISBN); 9783540690450 (ISBN) Momtazi, S ; Kafi, S ; Beigy, H ; Sharif University of Technology
    2008
    Abstract
    An stochastic version of the classical shortest path problem whereby for each node of a graph, a probability distribution over the set of successor nodes must be chosen so as to reach a certain destination node with minimum expected cost. In this paper, we propose a new algorithm based on Particle Swarm Optimization (PSO) for solving Stochastic Shortest Path Problem (SSPP). The comparison of our algorithm with other algorithms indicates that its performance is suitable even by the less number of iterations. © 2008 Springer-Verlag Berlin Heidelberg  

    Efficient semantic based search in unstructured peer-to-peer networks

    , Article 2nd Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, 13 May 2008 through 15 May 2008 ; 2008 , Pages 71-76 ; 9780769531366 (ISBN) Mashayekhi, H ; Habibi, J ; Rostami, H ; Sharif University of Technology
    2008
    Abstract
    Peer-to-peer networks have gained a tremendous popularity in sharing huge volumes of data. Success of such networks highly depends on the performance of their search algorithm. We propose a semantic based search algorithm for unstructured peer-to-peer networks. In the proposed method we establish ontology based indexes for outgoing links of each node, which are utilized in routing the query through the network. In contrast to available approaches, we maintain limited size indexes and also consider number of documents accessible via each link and the distance between source and destination nodes, to improve the accuracy and efficiency of our algorithm. Our design is scalable and adaptable, to... 

    Virtual point-to-point links in packet-switched NoCs

    , Article IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008, Montpellier, 7 April 2008 through 9 April 2008 ; 2008 , Pages 433-436 ; 9780769531700 (ISBN) Modarressi, M ; Sarbazi Azad, H ; Tavakkol, A ; Sharif University of Technology
    2008
    Abstract
    A method to setup virtual point-to-point links between the cores of a packet-switched network-on-chip is presented in this paper which aims at reducing the NoC power consumption and delay. The router architecture proposed in this paper provides packet-switching, as well as a number of virtual point-to-point, or VIP (VIrtual Point-to-point) for short, connections. This is achieved by designating one virtual channel at each physical channel of a router to bypass the router pipeline. The mapping and routing algorithm exploits these virtual channels and tries to virtually connect the source and destination nodes of high-volume communication flows during task-graph mapping and route selection... 

    Scalable architecture for a contention-free optical network on-chip

    , Article Journal of Parallel and Distributed Computing ; Volume 72, Issue 11 , 2012 , Pages 1493-1506 ; 07437315 (ISSN) Koohi, S ; Hessabi, S ; Sharif University of Technology
    2012
    Abstract
    This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical... 

    On the effect of random network coding in GIA-based P2P live video streaming systems

    , Article 2010 5th International Symposium on Telecommunications, IST 2010, 4 December 2010 through 6 December 2010 ; 2010 , Pages 657-662 ; 9781424481835 (ISBN) Ayatollahi Tabatabaii, H. S ; Khansari, M ; Rabiee, H. R ; Sharif University of Technology
    Abstract
    Recently it has been shown that network coding can highly improve the network throughput in the communication systems and specifically increase the downloading performance in P2P networks. This paper presents a new live streaming system for GIA-based P2P networks. In the proposed system the traditional GIA protocol is improved for an efficient use in multimedia applications. We introduce a new mesh-pull layered video streaming framework for GIA-based systems and employ random network coding to improve the network performance. Random network coding algorithm enables each peer to send a single encoded video chunk instead of multiple video blocks toward the destination node and save its...