Sharif Digital Repository

This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This approach is based on the differential configuration for the quantizer while maintains its inherent dynamic element matching property. Consuming no additional power and area compared to the conventional scheme, this architecture can eliminate the even orders of harmonic distortion and achieve higher linearity. Theoretical analysis for signal to quantization noise, power and area consumption and mismatch effect is provided. To illustrate the effectiveness of the new architecture in continuous time modulators, a modulator with 640 MHz sampling rate utilizing the mentioned quantizer is simulated in... 

A new single-bit cascaded 2-2 σ/δ (Sigma-Delta) modulator with only two op-amps, instead of four ones in conventional modulators, to decrease the static power consumption and area, is designed for GSM transceiver applications. The circuit consists of two new single op-amp, second-order, and low-pass loop filters to achieve a fourth-order quantization noise shaping. The modulator shows 84dB DR (Dynamic Range) for GSM signal bandwidth, while consuming 2.3mW from a 2.5V supply voltage. © 2003 IEEE  

This paper presents the design and implementation of a low power, low voltage, continuous time delta sigma modulator for audio band in 90 nm CMOS technology. A VCO-based integrator and quantizer are used. Inherent dynamic element matching (DEM) of the quantizer eliminates the need for explicit DEM logic which results in a short excess-delay and power saving. Simulation results show that the modulator achieves 78 dB SNDR and 87 dB SNR in a 20 kHz input bandwidth and dissipates 106 μW from 1 V supply. The power consumption for different parts is discussed  

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a... 

The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of... 

An area and power-efficient second order sigma-delta modulator is presented. At system level, we propose a new single-loop single-stage modulator that uses only one class-AB op-amp to realize a second order noise shaping for speech band applications. The modulator shows 86 dB DR in 4 kHz speech bandwidth. It consumes 125 μw from a 2.5 V supply  

This paper presents a new single-loop single-stage second order sigma-delta modulator. The circuit based on switched capacitor components just uses one Op-Amp to realize second order noise shaping. The modulator demonstrated 85 dB DR in 8kHz bandwidth, dissipating 135 μW from a 2.5 V supply. © 2002 IEEE  

A reduced complexity third-order digital delta-sigma modulator is presented. The modulator consists of two cascaded sections to produce proper shaping of quantization noise with minimum hardware. A new architecture for a digital third-order delta-sigma modulator based on Ritchie structure is proposed. The measurement results show 94dB SNR and 65% dynamic range  

A new second order sigma delta modulator with the reduced number of op-amps, to decrease static power consumption and area, is presented for voice band applications such as codecs. This switched capacitor modulator uses reused capacitor technique to reduce the input thermal noise and circuit area. It improves the DR of modulator by almost 0.5 bit. The modulator shows 87 dB DR for voice band while consuming 125 μW from a 2.5 V supply. © 2003 IEEE  

A single-chip Integrated circuit of 3.3 V/1 W class-D high fidelity and high efficiency audio power amplifier is presented in this paper. The design has been done using a 3.3 V/0.25 /spl mu/m CMOS process. The maximum output power is 1 W before the amplifier saturates. The THD+N at 0.5 W output power is below 0.03% and efficiency is better than 90% thanks to the careful design of the output stage. The dynamic range is more than 100 dB suitable for high fidelity audio applications. A single-loop single-bit third order sigma-delta modulator is used to generate the PWM signal from input audio signal. The PWM signal is then filtered at the output with a second order low pass filter external to... 

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous... 

A novel sturdy multi-stage noise-shaping sigma-delta modulator that cancels the first-stage quantisation error at the output of the modulator is presented. Since any stage of the modulator has unity signal transfer function, the modulator would be very robust to circuit non-idealities such as finite op-amp gain. Furthermore, the signal processing timing issue in the critical paths of the proposed topology has been relaxed due to shifting the delay of the last integrator to the feedback path of the modulator. Moreover, this topology can be implemented in the circuit level by a fewer active blocks. Therefore, it practically would be suitable for low-voltage and low-oversampling applications.... 

Stable and unstable limit cycles are important orbits in chaotic systems. So many works are done to find and to quench chaos by stabilizing them. In this paper a new family of limit cycle orbits around the Moon is introduced as a result of restricted three-body problem. The family is completely spatial and can be used as an out-of-plane velocity magnifier. Lyapunov exponent in the Floquet theory has also been checked and stability of the orbits has been measured  

Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

Purpose - Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach - This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N-d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules... 

A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two subblocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full... 

Nowadays, dynamic analysis of air-conditioner units is essential to achieve satisfactory comfort conditions in buildings with low energy consumption and operation cost. In this paper, a nonlinear multi input-multi output model (MIMO) of an air-handling unit (AHU) is considered. In the presence of realistic harmonic disturbances, nonlinear dynamics of AHU is investigated. The effect of various thermodynamics and geometrical parameters on limit cycles behaviour of the indoor temperature is investigated. It is observed that the indoor space volume plays as the bifurcation parameter of the system. Decreasing the indoor space volume leads to the occurrence of secondary Hopf (Neimark) bifurcation...