Sharif Digital Repository

This paper scrutinizes faults in a CAN controller that may result in masquerade failures, and suggests an even parity mechanism to detect them with minimum hardware overhead. To do this, a CAN controller is modeled by VHDL at behavioral level and is exploited to setup a CAN-based network composed of two nodes. A total of 5,500 faults are injected into essential parts of one of the controllers. The results show that about 3.44% of faults terminate in masquerade failures. The results, also, show that Register bank in the CAN controller are the most sensitive portions in which 92.10% of faults occurring in the Register bank result in masquerade failures. The even parity mechanism detects about... 

In this paper, we present an MPEG-2 video decoder implemented in our ODYSSEY design methodology. We start with an ASIP tailored to the JPEG decompression algorithm. We extend that ASIP by required software routines such that the extended ASIP can now perform MPEG2 decoding while still benefiting from hardware units common between JPEG and MPEG2. This demonstrates the ability of our approach in extending an already manufactured ASIP, which was tailored to a given application, such that it implements new, yet related applications. The implementation platform is a VirtexII-Pro FPGA. The hardware part is implemented in VHDL, and the software runs on a PowerPC processor. Experimental results show... 

During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5,... 

This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks... 

We unify virtual-method despatch (polymorphism implementation) and network packet-routing operations; virtual-method calls correspond to network packets, and network addresses are allocated such that routing the packet corresponds to dispatching the call. As the run-time routing structure is inherent in Network-on-Chip platforms, this unification implements polymorphism/or free.1  

Fuzzy inference systems always suffer from the lack of efficient structures or platforms for their hardware implementation. In this paper, we tried to overcome this difficulty by proposing a new method for the implementation of the fuzzy rule-based inference systems. To achieve this goal, we have designed a multi-layer neuro-fuzzy computing system based on the memristor crossbar structure by introducing a new concept called the fuzzy minterm. Although many applications can be realized through the use of our proposed system, in this study we only show how the fuzzy XOR function can be constructed and how it can be used to extract edges from grayscale images. One main advantage of our... 

Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported  

We present a design and implementation of a high-throughput deep packet inspection performing both stream categorization and intrusion detection on GPU platform using CUDA. This implementation is capable of matching 64 ethernet packet streams against 25 given regular expressions at 524 Mb/s rate on a computer system with GeForce GTX 295 graphic card  

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

In this paper, we integrate an assertion-based verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification. In this direction a system-level assertion language is defined. The system-level assertions can be used to monitor the current state of system or flow of transactions. These assertions are automatically converted to "monitor hardware" or "monitor software" during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertions, and hence, can be reused to verify the... 

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of... 

Hardware prefetching schemes which divide the misses into streams are generally preferred to other hardware based schemes. But, as they do not know when the next miss of a stream happens, they cannot prefetch a block in appropriate time. Some of them use a substantial amount of hardware storage to keep the predicted miss blocks from all streams. The other approaches follow the program flow and prefetch all target addresses including those blocks which already exist in the L1 data cache. The approach presented predicts the stream of next miss and then prefetches only the next miss address of the stream. It offers a general prefetching framework, two-phase prediction algorithm (TPP), that lets... 

In this paper we introduce a mathematical modeling tool (called Classic General Model: CGM) for the general problem of hardware-software codesign so that different partitioning algorithms can be easily and quickly developed and compared in this same framework. CGM introduces a simple but efficient model which supports single/multiprocessor, primal and dual approaches, fine or coarse granularity. CGM determines solutions by stating Mapping, Implementation and Permutation arrays. For judging among solutions of a certain algorithm, an Objective Function is defined. After modeling the problem by CGM we have a classic problem: finding the best values for elements of three arrays to optimize the... 

To enhance the error detection capability in COTS (commercial off-the-shelf) -based design of safety-critical systems, a new hardware-based control flow checking (CFC) technique will be presented. This technique, Control Flow Checking by Execution Tracing (CFCET), employs the internal execution tracing features available in COTS processors and an external watchdog processor (WDP) to monitor the addresses of taken branches in a program. This is done without any modification of application programs, therefore, the program overhead is zero. The external hardware overhead is about 3.5% using an Altera Flex 10K30 FPGA. For different workload programs, the execution time overhead and the error... 

Data cache hit ratio has a major impact on execution performance of programs by effectively reducing average data access time. Prefetching mechanisms improve this ratio by fetching data items that shall soon be required by the running program. Software-driven prefetching enables application-specific policies and potentially provides better results in return for some instruction overhead, whereas hardware-driven prefetching gives little overhead, however general-purpose processors cannot adapt to the specific needs of the running application. In the application-specific processors that we develop customized to an object-oriented application, we implement application-specific hardware... 

System fault-tree analysis is a technique for modeling dependability that is in widespread use. For systems such as embedded systems that include both hardware and software, the integration of hardware and software fault trees has proved problematic. In this paper, we present a method for reliability and safety analysis of embedded systems modeled by SystemC language. The evaluation is based on the fault trees generated from both hardware and software parts of the embedded systems described in the unified language. The unified modeling of both hardware and software of embedded systems using SystemC enables designers to be early aware from the safety and reliability of their designs more... 

This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest pans of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Co-operation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject... 

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform... 

In an introductory course of computer architecture, it is of high value that students use a simple and special CPU designed for this purpose and also its graphical simulator for better understanding of the computer hardware operation. In this paper, we present Abu-Reiahn, a simple 8-bit processor which we have specifically designed and built as the introduction part of computer architecture course to help students familiarize with hardware and software of a real CPU. Effective use of our computer graphical simulator along with the hardware allow the students to deepen their knowledge of logic circuits and the need for desired timing signals in a CPU to perform specific tasks  

While performance and power consumption of processors present a classic trade-off in designing embedded hardware, software can be optimized in favor of both performance and energy. We evaluate the impact of optimizations at different stages of designing embedded software. We show that algorithm choice and compiler optimizations aimed at improving performance can also reduce energy consumption of an embedded processor. We also propose energy-aware compilation guidelines which can further reduce energy consumption without performance penalties. Our experimental results show that up to 85% energy reduction and 89% performance improvement can be achieved by these techniques