Sharif Digital Repository

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

This paper presents a new high speed current mirror with continuous gain adjustment. Based on this current mirror, a variable gain current amplifier is designed in 0.18μm CMOS technology. The current gain of the amplifier can be continuously varied from 0 dB to 20 dB while the bandwidth of the circuit remains above 1.00 MHz. The circuit consumes 0.9 mW from 1.5V supply. © IEICE 2007  

This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

A novel, precision current reference with low temperature and supply sensitivity and without any external component has been designed in a 0.18μm CMOS mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit like a beta multiplier. The simulation results show max-to-min fluctuation of about 1% over a temperature range of -20°C to +100°C and supply voltage range of 1.1V to 2V with ±30% tolerance for all of the used on-chip resistors. The maximum nominal current variation in process corners is less than 3.5%. © 2003 IEEE  

A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The... 

The design strategy and efficiency optimization of UHF micro-power rectifiers using a novel diode connected MOS transistor is presented. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduce the threshold voltage and leakage current in compare to conventional diode connected transistors. Using the proposed diode in typical rectifiers makes a significant improvement in output voltage and current therefore the efficiency is increased comparing to the same rectifier architectures using conventional diodes. Also a design procedure for efficiency optimization is presented and a superposition method is used to optimize the performance of multiple output... 

An analytic method for prediction of oscillation amplitude and supply current of differential CMOS oscillators is presented. The validity of this method has been verified by designing an LC CMOS oscillator in a 0.24 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage  

A low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.25um CMOS technology, with a power supply of 1 volt. The results show PSRR is below -70dB at 1MHz and the output voltage variation versus temperature (0-70) is less than 0.3%. This circuit shows robustness against process variation  

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM  

A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE  

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

A very low power CMOS, 1.5V, 2.5GHz prescaler was designed. Implemented in 0.25u standard CMOS technology, this prescaler can operate up to 3GHz range. The prescaler consists of three delay flip flops (DFF) that work synchronously with RF sinusoidal clock and divides by 4 or 5 according to control signal  

A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE  

A 4th order, 5 MHz, lowpass Butterworth Gm-c filter has been combined with a low noise low-voltage amplifier to form a lowpass filter for video applications. In this filter an improved transconductor and a powerful method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the filter is -77 dB for 1 Vppd input signal. Input referred noise is 40 nV/√Hz in the worst case. All the circuits are designed based on a 0.25 μm CMOS process technology with a single 1.8 V supply. © 2002 IEEE  

In this brief, a transformer-type power combiner for a fully integrated high-power CMOS power amplifier (PA) is presented. The proposed power combiner is composed of a number of transformers that, unlike the ones in conventional approaches, have different sizes. This leads to higher efficiency and smaller chip area. After considering several power stage topologies, analysis and optimization of the transformer network (the power combiner) are presented. To demonstrate the advantages of the proposed architecture, a 900-MHz CMOS PA with the proposed power combiner was implemented with a 0.18-μm radio-frequency CMOS process. The amplifier achieved an efficiency value of 24% at the maximum output... 

In this paper a self-oscillating mixer is presented fundamental signal generated by the oscillator subcircuit in the mixing process. The oscillator core consumes 3mA of current from a 1.8 V DC supply and results in an output power of -0.867 dBm per oscillator, and a measured phase noise of -91, -102 and -108 dBc/Hz at 100 KHz, 600 KHz and 1 MHz from the carrier, respectively. In the mixing process the proposed mixer achieved IIP3 of 0 dBm with conversation gain of 1.93 dB. The circuit was designed and simulated in 0.18-μm CMOS technology by ADS2010  

A very low-power RF front-end based on a new current reuse QLMV cell (Quadrature VCO-LNA-Mixer) is proposed for GPS applications. The front-end, designed in 0.18μm CMOS technology, provides improved performance characteristics while consuming only 1 mA current. Simulation results are presented and compared with recently published works in the field  

In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA... 

An X-band core chip is designed and fabricated in 0.18-μm CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, each of which includes a 6-b phase shifter, a 6-b attenuator, along with two input and output amplifiers. A new architecture for realizing such a core chip system and a low loss circuit for 5.625° phase shift block are proposed. The overall rms phase and gain errors are better than 2° and 0.25 dB, respectively, in both RX/TX paths. The gain of each path is around 12 dB, while the output 1-dB compression point is higher than 10 dBm over the... 

Rectifiers are an integral part of power harvesting systems. In this paper, the literature on RF power rectifiers is surveyed, starting from the well-known voltage doubler. Effects of using low turn-on voltage devices on forward and reverse losses, and therefore, on conversion efficiency, is discussed. Samples of rectifiers with external devices, such as Schottky diodes are presented. Idea of external Vth cancellation through a rechargeable battery, self Vth cancellation, and floating gate transistors with charge injection onto the gates are demonstrated. Then, standard bridge rectifier and its modified versions, including Vth cancellation technique, are explained. Using low voltage devices...