Sharif Digital Repository

A Brillouin probing method is proposed to extract the distribution of signal power along phase-sensitive parametric amplifiers. Operation near the zero-dispersion-wavelength shows enhanced sensitivity to dispersion fluctuations, allowing effective extraction of the dispersion map  

The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-ampli-fication phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%  

A PC-based digital lock-in amplifier was implemented completely in software (Labview) for photoplethysmograph (PPG) measurement. Experiments carried out to evaluate the performance of the amplifier show that the system can recover the signals up to 40 dB below the interference (ambient light). This system can be customized later to measure the trans-abdominal PPG signal of pregnant women for fetal heart rate detection. ©2007 IEEE  

In this paper, the transient response of a double coupler fiber ring resonator containing an erbium-doped fiber amplifier (EDFA) in half part of the fiber ring resonator and a quantum dot-doped fiber (QDF) saturable absorber in the other half, is investigated. It is demonstrated that, depending on the device parameters and the input power of the signal and pump, various types of dynamic behaviors (such as bistability, monostability, and regenerative pulsation) can be observed in this intrinsic, optical bistable device. The proposed device can be exploited by optical communication networks to realize all-optical functionalities  

This paper presents a capacitor cross-coupled gm-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13 μm CMOS technology illustrates near 1.7 dB improvement in the circuit sensitivity and 5.2 dB enhancement in transimpedance gain compared to its... 

A 1.8V, 10-Bit, 40-MS/s Pipeline analog-to-digital converter designed using 0.18-μmCMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free- dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5mW.... 

A new approach for the design of two-stage Miller-compensated CMOS op amps is presented. The paper studies the basic relations between power consumption, unitygain bandwidth, the biasing region, technology parameters, and the external capacitive load. As a result, simple and efficient design guides are provided to achieve the minimum possible power consumption for the given specifications and for short-channel devices. It is shown that the conventional design procedures do not always result in minimum power op amps. The presented results are also verified by Spectre simulations  

A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a... 

A 37 dBm power amplifier (PA) is designed on a 0.25 μm optical T-gate pseudomorphic high electron mobility transistor (pHEMT) technology. The design of this two-stage PA along with a step-by-step design procedure is presented in this paper. This methodology can be used for design of PA in different technologies and frequencies. The PA delivers 5 W output power over the frequency band of 13-19 GHz. It shows average power-added efficiency of 37% and large signal gain of 15 dB in measurements which is consistent with simulation results. The output power and efficiency of the realised amplifier reach maximums of 37.6 dBm and 45%, respectively. Considering output power, bandwidth, chip area and... 

This paper presents a bandwidth enhancement technique for broadband Darlington amplifiers. A detailed analysis of the high-frequency performance of the Darlington amplifier and the effect of bandwidth enhancement is provided. A design procedure is also given for broadband feedback Darlington amplifiers with bandwidth enhancement and gain flattening. A single- and a three-stage feedback amplifier with the proposed improvements are designed and implemented in a 0.25-μm Al-GaAs-InGaAs pHEMT technology. The single-stage amplifier provides 6 ± 0.4 dB of small-signal gain in the frequency band of 1-30 GHz. The three-stage amplifier features 17.8 ± 0.8 dB of small-signal gain in the frequency band... 

Theoretical stability analysis of broadband cascode amplifiers at high frequencies is presented. The stability of the amplifier in the presence of parasitic inductive components is thoroughly investigated. It is shown that the stability can be improved by inserting a series resistance in the gate of common-gate device of the cascode amplifier. To ensure stability, the gate resistance should be selected within specific ranges that are derived analytically. Based on the insights provided by the analyses, several practical design guidelines are given to improve the stability of high-frequency broadband cascode amplifiers. Finally, the derived results are adopted in stabilisation of an X-band... 

In spite of the recent steady increase of the volume of the second-hand markets, often customers remain in doubt regarding the quality and durability of the secondhand products. Aiming to reduce and share this uncertainty, dealers offer warranty on their products. Offering warranty for second-hand products is a relatively new marketing strategy employed by dealers of used electronic equipment, furniture, automobiles, etc. Usually, for used products, the dealer's expected warranty cost is a function of product reliability, past age and usage, servicing strategy and conditions and terms of the warranty policy/contract. Sometimes the offered policy is limited by two parameters, typically the... 

An X-band core chip is designed and fabricated in 0.18-μm CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, each of which includes a 6-b phase shifter, a 6-b attenuator, along with two input and output amplifiers. A new architecture for realizing such a core chip system and a low loss circuit for 5.625° phase shift block are proposed. The overall rms phase and gain errors are better than 2° and 0.25 dB, respectively, in both RX/TX paths. The gain of each path is around 12 dB, while the output 1-dB compression point is higher than 10 dBm over the... 

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel... 

A highly linear X-band low-noise amplifier (LNA) is proposed and implemented in a standard 0.18-μm CMOS technology. The LNA features both high and low-gain operation modes. In its normal high-gain mode, the LNA shows a small-signal gain of 13.6 dB with an IIP3 of +9.5 dBm and a noise figure of 4.7 dB. The two-stage amplifier draws 90 mA from the 3.3V power supply to achieve +14.8 dBm output P1dB (+2.2 dBm input P1dB). In the low-gain mode, the gain is reduced by about 10 dB to further enhance the linearity and to accommodate very large blockers. Accordingly, the input P1dB is enhanced to +13.7 dBm while the noise figure is increased by 8.1 dB. A technique is also introduced to maintain the... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE  

Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012... 

A PWM controlled class-D amplifier generates harmonics at switching frequency and its multiples. In this paper, the Random PWM (RPWM) technique is applied in order to spread the noise spectrum over a wide range, thus, considerably reducing amplitudes of these harmonics and the consequent EMI problems. A Line Impedance Stabilization Network (LISN) is used to study the RF noise emanating from the converter. Simulation and experimental results confirm the validity method and demonstrate the effectiveness of applying the RPWM technique in reducing the RF noise level