Sharif Digital Repository

A sampling and switching method for a binary weighted digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. This sampling method is proposed to reduce the switching energy. Thanks to the proposed switching method, only one reference voltage (Vcm = 1/2 Vref) is required which helps to improve the precision of the DAC along with energy reduction compared with those methods that use more than one reference voltage. The switching energy and area of the DAC reduce by 97.66% and 50% compared with the conventional binary weighted DAC  

The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

An ultra-efficient switching method for successive approximation register ADCs is proposed. In this method, the input signals are sampled in a special fashion to reduce the switching energy. Owing to the sampling method, only one reference voltage (Vq=Vref/4) is required to implement the switching steps. Therefore, in addition to reduction in the switching energy (due to the lower supply voltage), the precision of the DAC is improved. The proposed method reduces the switching energy and area by 99.41 and 50%, respectively, compared with the conventional method. © 2016 The Institution of Engineering and Technology  

A highly energy-efficient switching method for capacitor-splitting digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. In the proposed DAC, a bottom-plate sampling method is introduced which requires only one reference voltage (Vcm = 1/2Vref) during the entire DAC switching steps. Therefore, in addition to the switching energy reduction, the precision of the DAC is increased since only one reference voltage is used. The DAC average switching energy and the area are reduced by 98.44% and 50% compared with the conventional binary weighted DAC  

A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©... 

This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s... 

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is... 

In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

We study the hydrodynamic dispersion (HD) by electroosmotic flow in soft microchannels. Considering a fully developed flow in a slit microchannel of low surface potential and adopting the Taylor dispersion theory, we derive analytical solutions for the solute concentration field and the effective dispersion coefficient. We also conduct numerical analyses to broaden the paper's scope to high surface potentials and to specify a criterion for the validity of the Debye-Hückel linearization in soft microconduits as well as to investigate the broadening of an analyte band from the time of injection. It is demonstrated that the effective dispersion coefficient of a neutral solute band is generally...