Sharif Digital Repository

All-solution-processed multilayer ZnO/Ag NWs/ZnO/PVP/PVA composite is introduced as a transparent conductive film (TCF) for optoelectronic applications. Unlike conventional film formation methods that impose high investment expenses, scalable spray coating is applied over the layers using a hand-made spray apparatus. The resulting TCF exhibits high transmittance (T, 86% at 550 nm) and low sheet resistance (Rs, 6 Ω/sq), which is comparable to the sputtered counterparts. The bending test demonstrates the flexibility of the multilayer TCF with no noticeable increase in Rs, even after 1500 bending iterations. Moreover, chemical stability test (exposure to a corrosive agent) and adhesion... 

Accidents involving falls and falling objects (group I) are highly frequent accidents in the construction industry. While being hit by a vehicle, electric shock, collapse in the excavation and fire or explosion accidents (group II) are much less frequent, they make up a considerable proportion of severe accidents. In this study, multiple-correspondence analysis, decision tree, ensembles of decision tree and association rules methods are employed to analyse a database of construction accidents throughout Iran between 2007 and 2011. The findings indicate that in group I, there is a significant correspondence among these variables: time of accident, place of accident, body part affected, final... 

In recent years, thin silver nanowires (Ag NWs) with diameters smaller than 150 nm have been synthesized by implementation of NaCl or FeCl3 as reaction promoters and high molecular weight polyvinylpyrrolidone (PVP) as the capping agent. However, the yield of Ag NWs still remains low, mostly due to the insufficient aspect ratio (AR) of the synthesized nanostructures and the production of Ag nanoparticles, which is an undesirable by product. This study proposes a modified technique to alleviate the problem by using a mixture of FeCl3/CuCl2 as the reaction promoter and two different types of PVP with molecular weight of 360 k and 40 k as the capping agents. The appropriate mixtures of... 

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults... 

This paper presents a fault injection tool, called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent faults into the Verilog as well as VHDL models of a digital circuit to study the fault behavior, fault propagation and fault coverage. Moreover, using specific simulators, the SINJECT provides a mixed-mode fault injection, i.e., fault injection into both Verilog and VHDL parts of a model, to achieve high description reality by Verilog and high capability modeling by VHDL. To demonstrate the tool, two case studies are evaluated: 1) an... 

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults... 

A Hub Location Problem (HLP) deals with finding the locations of hub facilities and assignment of demand nodes to established facilities. Hubs play a central role in many networks such as telecommunication networks and their unavailability may lead to network breakdown or poor service levels. An objective in design of a hub-and-spoke network is maximization of reliability to transfer flows. This paper puts forward design of a reliable single-allocation hub-and-spoke network using an interactive fuzzy goal programming. To model and solve the problem, a fuzzy goal programming approach was developed for design of network in an interactive manner between decision maker and the model. To validate... 

This paper addresses the multiple allocation hub set-covering problem considering backup coverage and mandatory dispersion of hubs. In the context of this paper, it has been assumed that a flow is covered if there are at least Q possible routes to satisfy its demand within a time bound. Moreover, there is a lower limit for the distance between hubs in order to provide a degree of dispersion in the solution. Mathematical formulation of this problem is given, which has O( n2) variables and constraints. Computational experiments carried out on the well-known CAB dataset give useful insights concerning model behavior and its sensitivity to parameters  

The maximal covering location problem (MCLP) is a challenging problem with numerous applications in practice. Previous publications in the area of MCLP proposed models and presented solution methodologies to solve this problem with up to 900 nodes. Due to the fact that in real-life applications, the number of nodes could be much higher, this paper presents a customized Genetic Algorithm (GA) to solve MCLP instances, with up to 2500 nodes. Results show that the proposed approach is capable of solving problems with a fair amount of exactness. In order to fine-tune the algorithm, Tukey's Least Significant Difference (LSD) tests are employed on a set of test problems  

Most of the publications regarding the maxim covering location problem (MCLP) address the case where the decision is to be made for one period. In this paper, we deal with a rather untouched version of MCLP which is called dynamic MCLP (DMCLP). In order to solve this problem, a simulated annealing (SA) has been presented. The proposed solution algorithm is capable of solving problems with up to 2500 demand nodes and 200 potential facilities with a fair amount of exactness. Our experiments showed that the proposed approach finds solutions with errors less than one percent  

SRAM-based FPGAs are currently utilized in applications such as industrial and space applications where high availability and reliability and low cost are important constraints. The technology of such devices is sensible to Single Event Upsets (SEUs) that may be originated mainly from heavy ion radiation. This paper presents a fault injection method that is based on emulated SEU on the configuration bitstrearn file of commercial SRAM-based FPGA devices to study the error propagation in these devices. To demonstrate the method, an Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used. A fault injection tool is developed to inject emulated SEU faults into the circuits.... 

The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device  

It is possible to define multiresolution by reversing the process of subdivision. One approach to reverse a subdivision scheme appropriates pure numerical algebraic relations for subdivision using the interaction of diagrams (Bartels and Samavati, 2011; Samavati and Bartels, 2006). However, certain assumptions carried through the available work, two of which we wish to challenge: (1) the construction of multiresolutions for irregular meshes are reconsidered in the presence of any extraordinary vertex rather than being prepared beforehand as simple available relations and (2) the connectivity graph of the coarse mesh would have to be a subgraph of the connectivity graph of the fine mesh. 3... 

We present the zero temperature phase diagram of the bond alternating Ising chain in the presence of Dzyaloshinskii-Moriya interaction. An abrupt change in ground state fidelity is a signature of quantum phase transition. We obtain the renormalization of fidelity in terms of quantum renormalization group without the need to know the ground state. We calculate the fidelity susceptibility and its scaling behavior close to quantum critical point (QCP) to find the critical exponent which governs the divergence of correlation length. The model consists of a long range antiferromagnetic order with nonzero staggered magnetization which is separated from a helical ordered phase at QCP. Our results... 

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

2,4,6,8,10,12-Hexanitro-2,4,6,8,10,12-hexaazaisowurtzitane (2,4,6,8,10,12-hexanitro-2,4,6,8,10,12-hexaazatetracyclo dodecane (CL-20)-based polymer/plastic bonded explosives are used in propellant formulation. It can be predicted that CL-20-based nano-polymer/plastic bonded explosives are able to have reduced composite sensitivity and superior mechanical strength. In the current study, we have prepared two kinds of CL-20-based nano-polymer/plastic bonded explosives with ethylene-vinyl acetate copolymer and glycidyl azide polymer via the microemulsion method. Several visual techniques such as SEM/AFM/TEM techniques have been utilized for complete characterization of CL-20-based... 

SRAM cache memories suffer from single event upset (SEU) faults induced by energetic particles such as neutron and alpha particles. To protect these caches, designers often use error detection and correction codes, which typically provide single-bit error detection and even correction. However, these codes have low error detection capability or incur significant performance penalties. In this paper, a protected cache scheme based on the variable associativity of sets is presented. In this scheme, cache space is divided into sets of different sizes with variable tag field lengths. The other remained bits of tags are used for protecting the tag using a new protection code. This leads to... 

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of... 

Information integrity in cache memories is a fundamental requirement for dependable computing. As caches comprise much of a CPU chip area and transistor counts, they are reasonable targets for single and multiple transient faults. This paper presents: 1) a fault detection scheme for tag arrays of cache memories and 2) an architectural cache to improve dependability as well as performance. In this architecture, cache space is divided into sets of different sizes and different tag lengths. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. The results show that error detection...